[SI-LIST] Re: PCI Express Reference Clock Question
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Joel Brown <joel@xxxxxxxxxx>
- Date: Tue, 07 Sep 2010 12:32:30 -0700
PCIe retimes from the data stream, so as long as the receiving PLL can
lock onto the transmitted data stream, and can lock quickly enough
clocking is not a problem. Since 100ppm clocks are cheap and readily
available, I wouldn't go with a looser spec than that.
Spread spectrum pushes the clock frequency around sufficiently that
given PCIe's very low frequency fundamental you would have to lock onto
and reproduce the SS modulation. In theory it can be done because the
characteristics of the SS clocking are defined. But you are restricted
to what is implemented in the silicon you can buy, or developing the
capability yourself. If you don't have considerable expertise in PLLs I
would avoid wandering into such territory unless you really have to.
One of the things that you would have to keep in mind is how you would
do your test qualification.
Steve.
Joel Brown wrote:
> I am working on a design where it would be desirable to not have to connect
> the PCI Express reference clock from the system (Intel chipset) to the
> device (i.e. graphics card).
> I have read briefly about using a separate reference clock at the system and
> device and that it must be 100 MHz +/-300ppm.
>
> I also understand that this will not work with spread spectrum clocking
> enabled.
>
> However I have not been able to find a definitive spec or white paper that
> goes into detail.
>
> In general will this work?
>
> Are there cases where it won't work?
>
> Does it make any difference if we are using Gen 1, Gen 2 or both?
>
> How common is it for PCI Express spread spectrum clocking to be needed to
> meet EMI requirements?
>
> Where can I find a specification or application note that covers this?
>
>
>
> Thanks - Joel
>
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--
Steve Weir
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