[SI-LIST] Re: PCI Express Reference Clock Question
- From: Mike Brown <bmgman@xxxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Wed, 08 Sep 2010 15:16:35 -0500
As Steve notes, the reference clocks do not need to be phase/frequency
locked if they are "close enough" in frequency to each other. The data
recovery loop in essence locks to the transmitting clock by extracting
data recovery clocks from the transmitted data transitions. The wider
the frequency separation between the reference clocks, the less margin
the data recovery process will have.
Reference tracking is needed for SSC.
Mike
- - - - -
steve weir wrote:
>It is neither phase nor frequency synchronous. If you don't have to
>track a SS clock, a sufficiently stable and accurate local clock will do.
>
>Steve.
>Stefan Milnor wrote:
>
>
>>And does the reference clock at the receive end have to have any
>>specific phase relationship with the clock used at the source end, or
>>can it be completely independent?
>>
>>You often see PLL clock buffers used to replicate the 100 MHz clock
>>used at the PCIe root. Will independent 100MHz clocks at the targets
>>work just as well?
>>
>>------------------------------------------------------------------------
>>*From:* si-list-bounce@xxxxxxxxxxxxx on behalf of steve weir
>>*Sent:* Tue 9/7/2010 12:32 PM
>>*To:* Joel Brown
>>*Cc:* si-list@xxxxxxxxxxxxx
>>*Subject:* [SI-LIST] Re: PCI Express Reference Clock Question - Email
>>found in subject
>>
>>PCIe retimes from the data stream, so as long as the receiving PLL can
>>lock onto the transmitted data stream, and can lock quickly enough
>>clocking is not a problem. Since 100ppm clocks are cheap and readily
>>available, I wouldn't go with a looser spec than that.
>>
>>Spread spectrum pushes the clock frequency around sufficiently that
>>given PCIe's very low frequency fundamental you would have to lock onto
>>and reproduce the SS modulation. In theory it can be done because the
>>characteristics of the SS clocking are defined. But you are restricted
>>to what is implemented in the silicon you can buy, or developing the
>>capability yourself. If you don't have considerable expertise in PLLs I
>>would avoid wandering into such territory unless you really have to.
>>One of the things that you would have to keep in mind is how you would
>>do your test qualification.
>>
>>Steve.
>>Joel Brown wrote:
>>
>>
>>>I am working on a design where it would be desirable to not have to
>>>
>>>
>>connect
>>
>>
>>>the PCI Express reference clock from the system (Intel chipset) to the
>>>device (i.e. graphics card).
>>>I have read briefly about using a separate reference clock at the
>>>
>>>
>>system and
>>
>>
>>>device and that it must be 100 MHz +/-300ppm.
>>>
>>>I also understand that this will not work with spread spectrum clocking
>>>enabled.
>>>
>>>However I have not been able to find a definitive spec or white
>>>
>>>
>>paper that
>>
>>
>>>goes into detail.
>>>
>>>In general will this work?
>>>
>>>Are there cases where it won't work?
>>>
>>>Does it make any difference if we are using Gen 1, Gen 2 or both?
>>>
>>>How common is it for PCI Express spread spectrum clocking to be
>>>
>>>
>>needed to
>>
>>
>>>meet EMI requirements?
>>>
>>>Where can I find a specification or application note that covers this?
>>>
>>>
>>>
>>>Thanks - Joel
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
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>>>
>>--
>>Steve Weir
>>IPBLOX, LLC
>>150 N. Center St. #211
>>Reno, NV 89501
>>www.ipblox.com
>>
>>(775) 299-4236 Business
>>(866) 675-4630 Toll-free
>>(707) 780-1951 Fax
>>
>>
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>>
>
>
>
>
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