[SI-LIST] Re: Optimal Power/ground lauout for a 2-layer PCB

  • From: "Nagel, Michael" <Michael.Nagel@xxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 6 Feb 2002 11:23:47 +0100

Adeel,

Your task does not fit into my definition of fun ...

Here my 2 cents:

1. The most sensible thing in my eyes is to separate analog and digital +5V 
   already at the connector and to run the analog voltage through a ferrite 
   bead or even a more elaborate filter depending on the application.

2. The required value is a typical one I know from neigboured VCC/GND planes
   in multilayer PCBs with thin substrates and a couple of holes because of
   vias. I do not have any simulations on that. Maybe somebody else will
turn
   up with the right values? Running a 2-layer PCB on that kind of frequency
   is not a sensible thing in my eyes ...

Hope the people charging you with this task will have a second thought on
the
specifications.

Best regards,
        Michael

Again - just my 2 cents :)

-----Original Message-----
From: Adeel Malik [mailto:AdeelM@xxxxxxxxxxxx]
Sent: Mittwoch, 6. Februar 2002 10:47
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Optimal Power/ground lauout for a 2-layer PCB


Hi All,
                 I have a task to design a  2-layer board with a very packed
circuitry and so, no luxury of  having the ground or power planes. The power
supplies provided to the board are +5V, -24V and -48V, through a DIN-96
connector.
I have two questions:
 
1. Digital components would be fed directly from +5V supply whereas I have
to generate +5V Analog (for Analog ICs)  from +5V supply. How should I do
that so that transients at +5V due to digital IC's are not coupled to +5V
Analog ?. 
 
2. Secondly, I require the impedance of power tracks not more than 0.1 Ohms
at frequencies upto 50MHz. What should be the optimum dimensions of these
tracks (+5V and its ground) ?.
 
Also I 'ld appreciate if someone can guide me to an Application/Design note
describing power/ground layout on a double-layer PCB for a multiple-supply
instrument.
 
I' ld be thankful to your response,
Regards,
Adeel Malik,
Senior Design Engineer,
Communications Enabling Technologies,
5-A Constitution Avenue,
Islamabad, Pakistan.
Tel: 92-51-2826160
Fax: 92-51-2827469
 


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: