[SI-LIST] Re: One decoupling cap per BGA power pin?
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: Anand.Kuriakose@xxxxxxxxxx
- Date: Tue, 13 Aug 2002 10:20:21 -0700 (PDT)
Anand - You had a couple of good questions the other day. I was tied
up with some other work and did not respond..
There has been a lot discussion on si-list about having one decoupling
capacitor per power pin of active devices. The problem is that micro
processors and some ASICs have 10's or 100's of power pins and there is
no way to place a decoupling capacitor at each pin location.
Actually, the "one cap per pin" rule should have been thrown out the
window when we advanced from double sided printed circuit boards and
"power trees" to using layers in the PCB dedicated to solid (or mostly
solid) power planes. This happened many years ago, but the old rule of
thumb (which served us nicely for a long time) has outlived it's
usefulness.
A good analogy can be made with water towers and pipes. Back when we
had a rural economy, every farmer had his own water tower to supply the
needs of his house and farm. This is like having one decoupling
capacitor per power pin.
But soon everybody moved to the city. The cities placed 10 or more
water tanks up on the surrounding hills and hooked all the houses and
businesses up to the water tanks with a network of pipes. This is like
power planes supplying power to one or more chips from 10's or 100's of
decoupling capacitors. Once you connect the chips up to the caps with
power planes, it is impossible to determine which capacitor is
supplying current to each chip. This would be like trying to determine
which water tank is supplying water to an individual house through a
well interconnected system of pipes. A similar analogy can be made
with electrical power generation from public service companies and the
power grid. From the power meter in your house, it is impossible to
determine the generation station your electricity came from, or
even which state. In California, we understand this.
The water (or power) system may be limited by the capacity of the tanks
or the capacity of the pipes. Imagine having a dozen huge water tanks
hooked up to the city through a garden hose. This is what you have on
a PCB if your power planes are undersized (too high of impedance, too
high of spreading inductance, thick dielectric between power planes).
You have plenty of energy stored in the decoupling capacitors but the
channel for the energy to limits the amount of power that can be
consumed by the chips.
The other extreme is to have a dozen milk cans on top of the hill
hooked up to the city through 12 inch pipes. This would be like having
very good thin dielectric power planes (with a fair amount of embedded
capacitance) but very little stored charge to bring to the power
consumers. The distribution system is capable of carrying an enormous
amount of water but will very quickly exhaust the supply in the small
water tanks.
The trick to power distribution design is having enough energy storage
on the PCB (in the form of capacitors with several time constants) and
having big enough transport system (the impedance and inductance of the
power planes) in order to channel the energy from where it is stored to
where it is consumed. All of the valves (capacitor ESR and mounting
inductance, BGA pin pattern, electronic package, etc) have to be sized
in order to not severely limit the flow of power from the capacitors to
the chips.
The concept of one cap per power pin has long outlived it's
usefulness. Come to think of it, the phrase "decoupling capacitor" has
outlived it's usefulness. A much better phrase would be "power
distribution capacitor."
We now have to think in terms of having enough stored charge on our PCB
in order to support the power needs of the chips until a DC to DC
converter can respond to power transients. We have to think in terms
of having sufficiently low impedance power planes to bus the power from
the cap locations (maybe 100's of them) to the power pins of our
BGA's. There is no way we will fit enough storage capacity for our
chips on the PCB within the BGA pattern. There no way to identify
which capacitor is decoupling which pin. The capacitors establish low
impedance power distribution system across a broad frequency range and
the power planes are the conduit to bring the power to the chips. The
whole system should be sized consistently or you might end up with a
weak link in your chain.
regards,
Larry Smith
Sun Microsystems
> From: ANAND KURIAKOSE <Anand.Kuriakose@xxxxxxxxxx>
> To: Larry Smith <Larry.Smith@xxxxxxx>
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Noise on BGA core voltage rail
> Date: Fri, 9 Aug 2002 10:43:57 -0700
> MIME-Version: 1.0
>
> Hi Larry,
>
> When decoupling huge BGAs, only few of the high frequency caps can
> be placed directly under the BGA yielding very low inductance b/n the BGA
> power/GND pin and the caps. This is done by placing vias facing out into
> the quadrants (i guess we call it offset via placement). But the remaining
> caps have to be and are placed around the periphery of the BGA. I do not
> know what better can be done in order to reduce the trace inductance b/n cap
> to BGA pin. Are there any other methods to reduce the inductance in the
> decoupling paths?
>
> I have one more question. Since there will be a huge number of
> power/gnd pins in BGA (assume 729-pin BGA) we cannot afford to place one
> high frequency decap per power pin. If the power pins in the 4 different
> quadrants of the BGA are decoupled unequally, will there be different levels
> of noise seen at power pins in the different quadrants?
>
> Anand.
>
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