[SI-LIST] Using Planar Capacitors

  • From: "Michael Smith" <michael@xxxxxxxxxx>
  • To: "'[SI-LIST]'" <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 13 Aug 2002 10:09:22 -0700


I am new to this list and am noticing a lot of discussion on using power
and ground plane layers sandwiched together to form a capacitor.  This
seems like a fantastic way to provide a low impedance high frequency
capacitor.  But I am wondering how this will adversely affect a signal
which is routed on either side of this capacitor.  How significant will
the impedance discontinuity seen by the ground return current be as the
signal changes coupling planes from power to ground. I am designing a
board with 2 power and 2 ground planes.  If I form these planes into
capacitor pairs, then every time a signal changes layers, it will couple
to a different plane causing an impedance discontinuity in the return
current.  Can someone give me a feel for how significant this effect is?
How can I calculate the impedance discontinuity as the signal passes
through a via and the return current has to pass through a bypass/planar
caps when the signal changes layers?

Thanks for your help,

Michael Smith
iZ Technology Corp.

To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
or at our remote archives:
Old (prior to June 6, 2001) list archives are viewable at:

Other related posts: