[SI-LIST] Negative Deterministic Jitter
- From: vinod ah <ah.vinod@xxxxxxxxx>
- To: SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Wed, 3 Jul 2013 15:16:35 +0530
Hi all,
I am measuring Rj, Dj & Tj for a saved .wfm format waveform of PCIe3
compliance pattern (modified PRBS-11 pattern). When i feed the pattern
to SIGTEST software available for PCISIG.com, i see Tj of 17.34ps, Dj
of -0.53ps & Rj of 1.27ps rms.
I am unable to understand on negative result of Dj. Is it possible to
have negative jitter ??
In clock jitter measurements, edge moving ahead is considered as +ve
jitter while edge moving behind is considered as negative jitter, but
how is that applicable to a PRBS sort of pattern.
Regards
Vinod A H
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