=20 Hello SI experts, I have to solve for a DDR interface issue when traffic is full bandwith (1Gb/s): DDR is then blocked and we can not access to it anymore.=20 Note that this "should not be" a card bug because it happens only on a few cards, about 2 or 3 protos among more than 100 cards.=20 FYI, the Controller is an Intel Network Processor IXP2400 and the DDR interface is running at 150MHz.=20 On one of the fail cards, I have soldered some wires (about 3" long) on a few signals (CS, WE, RAS, CAS, CK, DQS0 and DQ0) and attached 4 probes on CK, WE, DQS0 and DQ0. I have launched the full bandwith test on this card and observed that it is now running OK for more than 118 hours without failing!!=20 The scope signals are very poor on the scope (scope + probe bandwith > 6GHz) because of the too long wires and the ground connection which is very poor.=20 But I can not understand why the interface is running OK for more than 5 days, whereas it normally fails before 2 minutes of full bandwith test!! Has someone already experienced such a case?=20 Could you please explain if some stubs on signals could make the signal integrity better, or ameliorates a timing, or so ...=20 Please remember that only 2 or 3 cards among more than 100 have this issue, which means that it "should not" be a design issue.=20 Thank you for your help, Regards,=20 Jean-Pierre.=20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu