[SI-LIST] Re: NPU / DDR interface bug issue
- From: "Kotson, Michael" <mkotson@xxxxxxxxxxx>
- To: <Jean_Pierre.Bouthemy@xxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>, <si-list-bounce@xxxxxxxxxxxxx>
- Date: Tue, 10 Apr 2007 09:48:34 -0600
Hi Jean-Pierre,
In addition, you might try Vref margining the DDR interface (without the
probes attached) on one of your working cards. This is done by varying
the Vref voltage from an external power supply while running a memory
test. Start at nominal voltage, and increment in steps (I usually use
10 mV steps) until you get a memory error. Do this in both the positive
and negative direction with nominal as your starting point and on both
your memory Vref and your memory controller Vref (but do them
independently, or you don't know which end caused the error). If you
only have 20-30 mV of margin, this is usually a pretty good indicator
that you have an SI, timing, or even a power issue. It's not uncommon
for a marginal signal to suddenly work when a probe is attached, due to
the change in circuit loading. Your chip supplier can probably provide
better guidance on what memory margin you should expect for your
particular processor.
Hope it helps,
Mike
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of BOUTHEMY JEAN PIERRE
Sent: Tuesday, April 10, 2007 8:18 AM
To: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
Subject: [SI-LIST] NPU / DDR interface bug issue
=3D20
Hello SI experts,
I have to solve for a DDR interface issue when traffic is full bandwith
(1Gb/s): DDR is then blocked and we can not access to it anymore.=3D20
Note that this "should not be" a card bug because it happens only on a
few cards, about 2 or 3 protos among more than 100 cards.=3D20
FYI, the Controller is an Intel Network Processor IXP2400 and the DDR
interface is running at 150MHz.=3D20
On one of the fail cards, I have soldered some wires (about 3" long) on
a few signals (CS, WE, RAS, CAS, CK, DQS0 and DQ0) and attached 4 probes
on CK, WE, DQS0 and DQ0. I have launched the full bandwith test on this
card and observed that it is now running OK for more than 118 hours
without failing!!=3D20
The scope signals are very poor on the scope (scope + probe bandwith >
6GHz) because of the too long wires and the ground connection which is
very poor.=3D20
But I can not understand why the interface is running OK for more than 5
days, whereas it normally fails before 2 minutes of full bandwith test!!
Has someone already experienced such a case?=3D20
Could you please explain if some stubs on signals could make the signal
integrity better, or ameliorates a timing, or so ...=3D20
Please remember that only 2 or 3 cards among more than 100 have this
issue, which means that it "should not" be a design issue.=3D20
Thank you for your help,
Regards,=3D20
Jean-Pierre.=3D20
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