The Altera Corporation, Characterization Group (Product Engineering) in San Jose, CA has multiple, immediate openings for Signal Integrity/Characterization Engineers. The job duties include characterizing complex FPGA with emphasis on high performance IO interfaces with their noise properties. The candidates will develop characterization strategies, plans, and schedules by integrating different requirements from various engineering and business departments. The candidates will execute device characterization which involves model extraction, simulation, hardware design bench measurements, and data analysis. Qualifications include a BSEE or equivalent with a minimum of 4 years experience. An in-depth knowledge of signal integrity is required. Experience of simulation with CMOS circuits in transmission line environments is required. Good written and oral communication skills are required. Knowledge of mixed-signal circuits such as PLL, CDR, and high-speed I/O buffers is a plus. Knowledge of high-speed I/O protocols such as PCI-Express, XAUI, and GigaBit Ethernet is desirable. An MSEE is a plus. Please forward your resume and contact information to Geping Liu gliu@xxxxxxxxxx or San Wong sanwong@xxxxxxxxxx ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu