[SI-LIST] Re: Matching differential traces
- From: Bill Owsley <wdowsley@xxxxxxxxx>
- To: wdowsley@xxxxxxxxx, EdiFraiman@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 17 May 2007 11:48:13 -0700 (PDT)
Yup, here is the empty note.
Now where was I... Oh yeah, in an ideal world, no wait, that can't be
right. (sound of a manual carriage return) start over
In an ideal world, the matched differential pair would sum to zero at all
points. Since that was so very long ago, we now live in a real world and we'll
find that these differential pairs do not match, or sum to zero at all points.
If this happens on the ethernet cable we'll find some degree of common mode
noise or EMI. This frequently will show up as energy at the clock frequency of
125 MHz, which is 100 MB due to 4/5 bit encoding. This mis-match can also be
described to some degree as a phase shift since one edge may move/transistion a
bit sooner than the other. Or it could just be from a difference in rising
edge shape vs falling edge shape. If phase shift or waveshape difference is
kept small enough, the non-zero sum will also be small, hopefully smaller than
the emissions limit. If it gets too big, not only can the limit be exceeded,
but the function, the eye, will not look so good and the bit error rate will go
up.
For pulling a number out of our collective ,,, uh?? air, then 1/10 of a edge
seems a good as any. Now that may not be enough, then it's the old iterative
game. Or instead, just go for all you can. The layout guys I work with match
trace lengths to less than a mil with about 45 seconds of effort. Well okay,
they knew I was going to ask for it so they came real close to begin with.
Some might say that's overkill - well it is free (nobody can point a finger at
a part) The edge shapes being driven out of the chips are another issue, and
with all the interesting techniques today for avoiding that problem, you'll
have to find out what your PHY is doing.
Oh, and ethernet uses some more stuff that makes 1/10, or 1/20, or 1/50 a
direction to head in. 100 MB along with 4/5bit encoding uses some multilevel
stuff, 3 levels if my memory leakage is not to bad. Then the 1 GB stuff uses
8/10bit encoding and 5 levels, all 4 pairs, and still runs at 125 MHz. So in
either case, the rail to rail voltage available is divided into multiple logic
levels. As interference, crosstalk, over/undershoot, etc. go so goes the bit
error rate, thus some effort at minimizing the mis-match.
BTW, if the MAC/PHY power/ground is messed up, the reference clock, 25 MHz?
will show up as will some of the digital traffic. And the 25 MHz is so
inconvenient when the data clock is 125 MHz, so watch the harmonics.
Bill Owsley <wdowsley@xxxxxxxxx> wrote:
Edi Fraiman wrote: Hi All,
My question is related to matching differential traces on PCB.
What the theoretical explanation to the next rule of thumb:
Matching between + to - of signal should be 1/10 of edge rate.
Best regards,
Edi Fraiman
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