Hi all, I am about to start a design based on the Xilinx Virtex-II Pro and I plan to use the RocketIO transceivers for board-to-board communication through and FR4 backplane. On one side of the board is the Xilinx FPGA and the rest will be full of ADCs sampling very sensitive analog signals with 16-bit resolution (1 LSB = 76 micro volts at the input of the ADC.) On the one hand the transceivers run at 3.125Gbps and at this frequency radiation can become a problem. But on the other hand, the higher the frequency, the more efficiently I can filter out any high frequency on the analog electronics. My questions are: 1) Is there any hope that my low-noise analog electronics will work untroubled by the high-speed links? 2) Apart from massive decoupling of the analog and digital parts, and shielding the serial links inside the backplane, is there any good hint I should follow? Regards and thanks for your help, Andreas _______________________________________________________ WEB.DE Video-Mail - Sagen Sie mehr mit bewegten Bildern Informationen unter: http://freemail.web.de/?mc=021199 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu