[SI-LIST] Re: Logic level at unused DQS
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: kbmanick@xxxxxxxxx
- Date: Thu, 17 Oct 2013 19:33:17 +0200
Hello,
if you don't have anydefined high/low level you might end up with some
midlevel while receiver are switched on. This could cause some
Crosscurrent through the receiver that you might not like.
This happens only during Writes to this device, so it is not normal ODT
that needs to be considered, but dynamic ODT. Are you have control if
this is enabled and which value is selected, or is this a flexible
feature in your system ?
Just as some theoretical thinkig: It depends on the logic implementation
of the devices what can happen. Usually the logic of the DRAM will count
DQS edges to get a "Write complete". The DRAM does not know that it
will get a non valid DQS (e. g. no edge at all or but many edges due to
midlevel). So if the logic in the DRAM will wait for completion of both
write bursts, or get one completion too early, what will happens ?
I don't think this is defined in the JEDEC spec, so you might get a
different behavior for different devices.
... I know such a configuration was used in the past for x16 ECC
implementations, but I have to admit I never thought about this ...
Hermann
Am 17.10.2013 08:47, schrieb Balamanikandan K:
> Hi
> In a x16 DDR3 device, DQ bus is comprised of two bytes. But I am using only
> one byte...let us say lower byte and unused DQ signals are left unconnected.
>
> In an ODT enabled condition, Why should I connect the unused DQS to
> ground through some resistor and unused DQS# to VDD through some
> resistor? Why should we bother about the logic level at unused DQS?
>
> My understanding is whatever it may be the logic level at unused DQS, it
> will not affect lower byte signals.
>
--
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Hermann Ruckerbauer
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Hermann.Ruckerbauer@xxxxxxxxxxxxx
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