[SI-LIST] Re: Logic level at unused DQS
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: Balamanikandan K <kbmanick@xxxxxxxxx>
- Date: Sun, 20 Oct 2013 14:39:54 +0200
Hello,
I guess it will not affect your lower channel Signals, but Cross Curent
in your Receivers can add some additional power consumption.
It should not be too much per Receiver, but I have no detailed numbers
how much this can be.
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
schrieb Balamanikandan K:
> Hi
>
> Thanks. But I could not understand "Cross Current". Also will it
> effect the lower byte signals?
>
>
> On Thu, Oct 17, 2013 at 11:03 PM, Hermann Ruckerbauer
> <Hermann.Ruckerbauer@xxxxxxxxxxxxx
> <mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx>> wrote:
>
> Hello,
>
> if you don't have anydefined high/low level you might end up with some
> midlevel while receiver are switched on. This could cause some
> Crosscurrent through the receiver that you might not like.
> This happens only during Writes to this device, so it is not
> normal ODT
> that needs to be considered, but dynamic ODT. Are you have control if
> this is enabled and which value is selected, or is this a flexible
> feature in your system ?
>
> Just as some theoretical thinkig: It depends on the logic
> implementation
> of the devices what can happen. Usually the logic of the DRAM will
> count
> DQS edges to get a "Write complete". The DRAM does not know that it
> will get a non valid DQS (e. g. no edge at all or but many edges
> due to
> midlevel). So if the logic in the DRAM will wait for completion of
> both
> write bursts, or get one completion too early, what will happens ?
> I don't think this is defined in the JEDEC spec, so you might get a
> different behavior for different devices.
> ... I know such a configuration was used in the past for x16 ECC
> implementations, but I have to admit I never thought about this ...
>
> Hermann
>
>
>
> Am 17.10.2013 08:47, schrieb Balamanikandan K:
> > Hi
> > In a x16 DDR3 device, DQ bus is comprised of two bytes. But I am
> using only
> > one byte...let us say lower byte and unused DQ signals are left
> unconnected.
> >
> > In an ODT enabled condition, Why should I connect the unused DQS to
> > ground through some resistor and unused DQS# to VDD through some
> > resistor? Why should we bother about the logic level at unused DQS?
> >
> > My understanding is whatever it may be the logic level at unused
> DQS, it
> > will not affect lower byte signals.
> >
>
>
> --
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de <http://www.EyeKnowHow.de>
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Itzlinger Strasse 21a
> 94469 Deggendorf
> Tel.: +49 (0)991 / 29 69 29 05
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
>
>
> --
> Best Regards,
> Balamanikandan.K
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