You are confusing the Intel problem of not referencing the GTL signal with
ground plane resulting in huge SSO noise with discussion of logic chassis
ground isolation.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lyndell Asbenson
Sent: Wednesday, May 9, 2018 2:10 PM
To: leeritchey@xxxxxxxxxxxxx; joel@xxxxxxxxxx; gurushankara@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Logic ground and chassis/safety ground
This is , and has been debated tons of times in the arena of high end
semiconductor test equipment. High end meaning > $3M/unit. I have seen tons of
book and tons of theory but, like most things in engineering it depends on what
your goals are?
Intel at one time had a big problem with its memory chip 1103 testing showed it
was good but when engineers attempted to use it, it was unreliable. David House
came to Intel from a systems background he solved the problem through 1000s of
experiments the solutions opened ended up requiring going from a 2 layer PCB to
4 layer PCB. Having power and ground planes on the inner layers, also requiring
caps .o1 .001 uf for noise decoupling etc.
-Regards,
Lyndell Lee Asbenson
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of leeritchey@xxxxxxxxxxxxx
Sent: Wednesday, May 9, 2018 10:12 AM
To: joel@xxxxxxxxxx; gurushankara@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Logic ground and chassis/safety ground
There is no electrical reason why you need to connect these two. If you do
connect them, do it in only one place and do it with a DC connection. I make
that connection on the side of the PCB where the unshielded wires exit as a way
to minimize potential EMI escaping on those unshielded wires.
Don't know where all of the rules of thumb come from about capacitors and
multiple connections.
Lee RItchey
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Joel Brown
Sent: Wednesday, May 9, 2018 9:47 AM
To: gurushankara@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Logic ground and chassis/safety ground
Unless you have a requirement or other reason to keep them isolated It would be
best to connect them together.
If you decide to keep them them isolated then add multiple capacitors between
signal and chassis ground at each chassis connection point that can be
populated with different value capacitors or zero ohm resistors. Another option
is to have a chassis ground plane layer in your PCB that is connected to signal
ground at multiple points with capacitors. If you don't have a solid RF
connection between signal and chassis ground then there can be an RF potential
between the two grounds that can radiate if you have antenna structures such as
slots in your enclosure or external cables.
Joel
On Wed, May 9, 2018 at 9:16 AM, Guru Shankara <gurushankara@xxxxxxxxxxx>
wrote:
Hi Experts,chassis.
I am working on a modem design that is powered by an AC/DC supply
(isolated).
The design includes a base board that hosts a mezzanine/daughter card
and both the baseboard and the mezzanine cards are powered by 12V DC.
The chassis walls and misc. mechanical hardware have a conductive
coating on the inside and will be connected to the
chassis/safety/earth ground of the AC/DC power supply.
As the name implies, the chassis/safety/earth ground provides for
safety of the operator if there is a situation where the higher
voltage side line of the AC/DC supply rips off and makes contact with
the
So, I prefer NOT to connect the board logic ground to the
chassis/safety/earth ground of the supply.
Any thoughts on if I should connect them together or not?
Also, if they need to be connected, is there a recommended method?
Really appreciate your help.
Thank you,
Gurushankar
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