[SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight?
- From: "Kenneth W. Egan" <kegan@xxxxxxxxxxxxx>
- To: <dp@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Sep 2005 23:05:42 -0500
Dimiter,
DDR-1 SDRAM's skew is for that device., i.e. a micron part, let's say,
indicates .4-.5nS skew, that's its potential worst case skew for the memory
device (outptut). The timing stack for the board would be memory--->
interconnect ---> memory controller (or other device ). So it may come down
to what's the skew tolerance of your memory controller, and design the
interconnect skew for the overall timing.
KWE
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Dimiter Popoff
Sent: Thursday, September 29, 2005 7:04 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Length matching of DDR-1 data lines - does it really have
to be that tight?
Hi everyone,
I found a number of appnotes on DDR-1 which state that data signals (and the
related, dqs and
dqm) must be length matched within +/- 50 mils. Now I read the spec of a DDR
chip I would use, and it says something like 0.4-0.5 nS max. skew between
these signals. At, say, 160 pS/inch, 50 mils means 8 pS .... Am I
overlooking something or are those recommendations I found just nonsense? (I
am talking the slowest, 133 MHz clock DDR, with up to 200 MHz in mind but
unnecessary for this particular design).
Thanks,
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
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