[SI-LIST] Length matching of DDR-1 data lines - does it really have to be that tight?
- From: "Dimiter Popoff" <dp@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 30 Sep 2005 03:03:30 +0300
Hi everyone,
I found a number of appnotes on DDR-1 which state that data signals (and the
related, dqs and
dqm) must be length matched within +/- 50 mils. Now I read the spec of a DDR
chip I would
use, and it says something like 0.4-0.5 nS max. skew between these signals. At,
say, 160 pS/inch,
50 mils means 8 pS .... Am I overlooking something or are those recommendations
I found
just nonsense? (I am talking the slowest, 133 MHz clock DDR, with up to 200 MHz
in
mind but unnecessary for this particular design).
Thanks,
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
