[SI-LIST] Re: LVDS to TTL converter
- From: Richard Jungert <r_jungert@xxxxxxxxxxx>
- To: Steven Kan <steven@xxxxxxxxxxxxxxxxxxxx>, <hariprasad.palli@xxxxxxxxx>, si list freelist <si-list@xxxxxxxxxxxxx>
- Date: Tue, 21 Jul 2009 19:45:36 -0700
Venkat.
In the telecom world in order to get from NRZ data ( clock and data ) to a bit
error analyzer 3 more circuits are needed in the main path. Here is how it
works for 45Mb/s DS3 US or 34Mb/s European Telecom data. The process is very
similar at 622MB/s OC-12.
1st start with: NRZ data ( scrambled ) signaling
2nd circuit: B3ZS Decoder circuit to RZ data ( data+ and data- with embedded
clock )
3rd circuit: RZ data to balanced 110 ohm to 75 ohm transformer and unity gain
buffer. With a 75 ohm output you can go to BER analyzer with 1 cable. This
signal is bipolar with embedded clock and DC balanced. The DS3 signal ready
for BER analyzer!!
The bit error analyzer has a the reverse signaling process ( with RZ to NRZ
Encoder ) to get back to NRZ data for BER analysis. One can also make a simple
bit error counter with NRZ data but this has to be implemented into the
scrambler circuit. ie: take the scrambler output and with 1 exclusive or gate
compare the scrambled data to incoming data to count single bit errors.
NRZ and scrambled DATA >> NRZ to RZ Decoder circuit >> Balanced RZ data to 75
ohm ( transformer ) circuit>> BER analyzer.
Here is an example of how to design a B3ZS encoder decoder circuit for 45Mb/s
to get the basic idea.
http://www.metatech.com.hk/appnote/teridian/pdf/wan/APP_B3ZSendec_v2-0.pdf
TDK semiconductor make this one.
Richard Jungert
> Date: Tue, 21 Jul 2009 13:54:56 -0700
> From: steven@xxxxxxxxxxxxxxxxxxxx
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: LVDS to TTL converter
>
> > Date: Sat, 18 Jul 2009 16:33:26 +0530
> > Subject: [SI-LIST] Re: LVDS to TTL converter
> > From: prasad <hariprasad.palli@xxxxxxxxx>
> > Hi Vignesh,
> >
> > thank you for reply. i am sorry that i mentioned TTL, which may not
> > work properly at higher frequency.
> >
> > my requirement is i have an analyzer systesm which does accept single
> > ended clock with data for BER measurement. But my device is having
> > Differential Clock, so i require a device which can covert LVDS to
> > single ended signal. that system is having 50ohm input for the clock
> > (with SMA connector).
> >
> > please suggest ...
> >
> > Best Regards, venkat
>
> Venkat,
>
> Thanks for the clarification. Translation to ECL might work. Are there
> separate CLK and DATA streams? Or is this data with embedded clock?
>
> If you have a DC-balanced signal (such as data with embedded clock) you
> may be able to AC-couple the resulting ECL signal into your analyzer.
>
> If you can't AC-couple (e.g. you have a random data stream), then you
> can use an ECL terminator.
>
> These types of terminators and translators are available from others as
> well, but as far as our products go you could use:
>
> 1) PRL-425N, Differential Receiver with NECL outputs. The outputs can be
> used differentially or single-ended, with the caveat that if you use the
> NECL output singly you will want to terminate the unused complement into
> an AC-coupled 50 Ohm load using our PRL-ACT-50. You can AC couple the
> required NECL output into your analyzer using our PRL-SC-104.
>
> 2) PRL-425N plus a PRL-550NQ4X. The latter unit provides proper NECL
> termination, plus DC level shifting so you can run it directly into a 50
> Ohm system.
>
> Please email me directly if you have more specific questions. Thanks!
> --
> Steven Kan (p) 310-515-5330 x24
> Pulse Research Lab (f) 310-515-0068
> 1234 Francisco St., Torrance, CA 90502 (c) 818-620-3062
> mailto:steven@xxxxxxxxxxxxxxxxxxxx
> http://www.pulseresearchlab.com
> Signal Buffering & Translation for Digital Design, Integration & Test
>
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