Hi Gang,
Got it; but whatâs confusing is that the spec has a section on RDQS mode
which suggests itâs an optional i.e DRAM doesnât have to send it.
My question then would be how is the gate training done if RDQS is not sent out
by the DRAM ?
Thanks,
Sparsh
On Jul 24, 2019, at 4:42 PM, Gang Zhao <phillypham@xxxxxxxxx> wrote:
Hi Sparsh,
It may be interpreted as the RDQS of DRAM can be generated from the Write
strobe WCK, in a way similar to LPDDR4 DRAM that the Read strobe is generated
from input clock.
BTW, the released LPDDR5 spec was not really a complete Rev1.0, with many
timing parameters left TBD. Some of the ambiguous writings like this could be
improved in the next release...
Gang
On Wed, Jul 24, 2019 at 4:22 PM Sparsh Patwa <patwa.sparsh@xxxxxxxxx> wrote:
Hi Gang,
But JEDEC spec says WCK is being used to clock write and read data; am I
missing something ?
Thanks,
Sparsh
On Jul 24, 2019, at 4:18 PM, Gang Zhao <phillypham@xxxxxxxxx> wrote:
WCK is the Write strobe; RDQS is the Read strobe.
Gang
On Wed, Jul 24, 2019 at 4:17 PM Sparsh Patwa <patwa.sparsh@xxxxxxxxx>
wrote:
Hello All,
Iâm trying to understand the new clocking architecture for LPDDR5 and
wanted to see if someone can explain what is the need for a RDQS mode when
the WCK can clock data on both write and read cycles ?
The Feb 2019 spec from JEDEC introduces WCK clocking and explains that the
CA bus operates at a lower clock CK where as the DQ bus operates off this
new WCK clock which can be 4x the speed of CK; and it can be used to
sample DQ for write and read operations however there is also a RDQS mode
where RDQS can be sent along with DQ during read cycles to same read data.
Maybe Iâm missing something here but why have WCK and RDQS if they are
used for the same purpose ?
Thanks,
Sparsh
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