Hello All,
I’m trying to understand the new clocking architecture for LPDDR5 and wanted to
see if someone can explain what is the need for a RDQS mode when the WCK can
clock data on both write and read cycles ?
The Feb 2019 spec from JEDEC introduces WCK clocking and explains that the CA
bus operates at a lower clock CK where as the DQ bus operates off this new WCK
clock which can be 4x the speed of CK; and it can be used to sample DQ for
write and read operations however there is also a RDQS mode where RDQS can be
sent along with DQ during read cycles to same read data.
Maybe I’m missing something here but why have WCK and RDQS if they are used for
the same purpose ?
Thanks,
Sparsh
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