[SI-LIST] Re: LPDDR2 derating table problem
- From: lei li <aleilee2008@xxxxxxxxxxx>
- To: "Hermann.Ruckerbauer@xxxxxxxxxxxxx" <hermann.ruckerbauer@xxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 17 Apr 2014 11:22:55 +0800
hi, Hermann
thanks for your reply.
But I didn't find related discussion in my email box.
do you have related information or links shown to me?
or anybody else can give me a hand on this topic?
BR
Lei
----------------------------------------
> Date: Wed, 16 Apr 2014 12:04:48 +0200
> From: Hermann.Ruckerbauer@xxxxxxxxxxxxx
> To: aleilee2008@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: LPDDR2 derating table problem
>
> Hello Lei Li,
>
> there have been several discussion on the list for this topic. Please
> search the archive, you should find some options/formulas to extrapolate
> the table.
>
> But especially the corner for the high slew rates is not really well
> defined (at least not for the commodity devices). DRAM and system
> vendors have been fighting for each ps for the slow slew rates .. nobody
> was really interested in the fast slew rate corners .. Usually you
> should have anyhow not problem with setup/hold with such fast slew rates
> (only if they cause reflections).
> I did not follow the discussion on LPDDR2 .. but somehow I doubt this
> was different to the discussions in commodity memory.
>
> Nevertheless I would recommend to check if you can slow down the slew
> rates e. g. by controller drivestrenght settings or even external serial
> terminaiton (if you have the space9. I would expect quite some
> overshoots and ringing with such high slew rates and also EMI might get
> worse.
>
> Hermann
>
>
>
> Latest Download:
> =================
> Presentation to our paper on the Embedded World Conference 2014:
> "Jitter in PCIe application on embedded boards with PLL Zero delay Clock
> buffer"
> http://www.eyeknowhow.de/en/downloads/
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
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>
> schrieb lei li:
>> Hi, Experts
>> There are tIS/tIH derating tables in JEDEC LPDDR2 standard (JESD209-2F) for
>> looking up. But in my project, the slew rate is out of the table.
>>
>> For example, in Table105, the maximum CK differential slew rate is 4V/ns,
>> and the maximum CA slew rate is 2V/ns. But my result is CK diff slew rate =
>> 8V/ns and CA slew rate = 4V/ns. They are out of the table list.
>>
>> My problem is how to ensure the derating value of tIS/tIH in my case.
>>
>> Thanks.
>>
>> BR,Lei Li ------------------------------------------------------------------
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>
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