[SI-LIST] Juniper Networks has another Signal Integrity Engineering Opening based in Sunnyvale, CA - Can I post this opening with you?
- From: Debra Smith <debsmith@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 2 Sep 2009 11:54:09 -0700
Signal Integrity Engineer - Digital or Mixed Signal
Sunnyvale CA
KEYS: High-speed, systems level SI, SerDes, Timing, Power Integrity, PCB
Technology
System level signal integrity and timing analysis on boards, packages, ASICs
and FPGAs.
- Design timing (setup/hold board timing analysis and clock design).
- Simulate and measure board level reflection, xtalk, ground bounce,
power/ground noise.
- Perform simulations for on-chip SI including core noise modeling, on chip
crosstalk, I/O selection, chip pinout assignment, package selection and pinout
assignment.
- PWB cross-section design/tradeoff, serdes channel analysis.
- Use lab equipment such as oscilloscopes, Time Domain Reflectometers, Vector
Network Analyzers, Spectrum Analyzers.
- Good lab debug skills.
- Proficient with HSPICE, Allegro, SiSoft, Speed2K, PowerSI, Ansoft HFSS.
- Good oral and written communication skills.
- Team player, willing to take on a variety of projects, good listening
skills, self motivator.
- 5 + years experience in SI with PhD preferred!
Debra Smith
debsmith@xxxxxxxxxxx
www.Juniper.com
408.936.4255
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