[SI-LIST] Hands-on Workshops from Agilent EEsof EDA: Ontario ON, Chelmsford MA, Minneapolis MN, Santa Clara CA, Anaheim CA

From: <colin_warwick@xxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Wed, 2 Sep 2009 12:55:35 -0600

Hi,

We're offering five complementary hands-on workshops entitled "Design Using 
Fast Channel Simulation and Statistical Eye Diagrams." Seating is limited: 
early enrollment is advised.
Details below.

Best regards,
-- Colin Warwick
Agilent EEsof EDA

==Title==
Design Using Fast Channel Simulation and Statistical Eye Diagrams

==Registration==
http://agilent.distributech.ca/registration.asp?seminarid=296 or 
http://bit.ly/iVesF 

==Abstract==
Signal integrity engineers need to determine ultralow BER contours for 
thousands of points in the design space in order to select the optimum set of 
characteristics for transmitter, channel, and receiver. Traditional techniques 
consume a prohibitively long simulation time. For this reason we've implemented 
a new statistical mode in our Channel Simulator that eliminates the need for 
long, multi-million-bit simulations. Now you can generate eye diagrams with 
ultralow BER contours in just a few seconds.
This in-depth, hands-on workshop will demonstrate the "what if" design space 
exploration workflow that our new statistical eye diagram channel simulator 
enables, and will also cover tools and modes that can be used in exceptional 
cases (e.g. equalizer adaptation, non-linearity, or specific bit patterns) 
where statistical eye techniques cannot be applied.
You will get first hand experiencing using signal integrity features that are 
new in ADS 2009 Update 1 and EMPro 2009, including equalizers, DDR compliance 
toolkit, and via simulation with 3DEM.

==Who should attend this workshop==
Signal integrity engineers for multigigabit links who are running into effects 
previously only seen in RF and microwave circuits.

==Dates & Locations==
September 15, 2009 - Ottawa, ON
September 22, 2009 - Chelmsford, MA
September 24, 2009 - Minneapolis, MN
September 29, 2009 - Santa Clara, CA
October 1, 2009 - Anaheim, CA

==Agenda==
All times are local
9:30a.m. - Register/Breakfast
10:00a.m. - Part 1
o ADS for signal integrity analysis 
o HSPICE netlist including W-element in ADS 
o Modeling and simulation of a PCI Express Gen2 channel using Channel Simulator 
in bit-by-bit and statistical mode 
o Equalizer, LMS, RLS, and ZF, and equalizer tap coefficient calculation 
12:00p.m. - Lunch
1:00p.m. - Part 2
o Channel optimization for eye diagram and BER 
o HDMI transmitter and how it can be modeled in ADS 
o DDR Compliance Toolkit 
o 3DEM simulation of a via model with EMPro 
3:00p.m. - End

Enroll today!
http://agilent.distributech.ca/registration.asp?seminarid=296 or 
http://bit.ly/iVesF 


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

[SI-LIST] Hands-on Workshops from Agilent EEsof EDA: Ontario ON, Chelmsford MA, Minneapolis MN, Santa Clara CA, Anaheim CA

Other related posts: