[SI-LIST] Job Opportunity
- From: "Pedro Gonzalez" <pedrog@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 18 Feb 2002 10:42:42 -0700
Location Silicon Valley, California
Department Hardware Engineering
Title Sr. Signal Integrity Engineer
Job Description
This engineer will work in the Graphics Processor Unit (GPU) hardware
engineering group. He/she will report to the Director of System Design and
be responsible for the design of graphics subsystems utilizing the company's
chip sets. The members that will be a part of this new group are outstanding
individuals that will need to handle challenging high speed designs, model
generation, verification and pre/post layout simulation and constraint
management of high speed digital busses. Work as part of a team with logic,
module designers, PCB and component engineers to characterize packages and
define termination strategies.
Primary area of responsibility:
This engineer will be responsible for the design of digital interfaces
connected to the GPU, including the Advanced Graphics Processor (AGP) bus,
Double Data Rate (DDR) memories, TV encoders, and 1394 phy chips. The design
process will include development of ASIC I/O cells, package substrates, net
topologies, termination schemes, board stackups, power distribution, bypass
decoupling, system timing spreadsheets, and routing documents.
Secondary area of responsibility:
* This engineer will work with a Board Design Engineer to power on, bring
up, debug, and validate the new product reference design, taking
responsibility for the design robustness over temperature, voltage, and
frequency.
Requirements
This engineer should be competent in the field of signal integrity and high
speed digital design where transmission line environments are common.
Previous design experience in a field which may include networking, graphics
or computer systems is necessary. Must be proficient with most signal
integrity simulation tools using SpecctraQuest, APSIM, HSPICE, and Model
validation software such as IConnect is preferred. A good knowledge of
transmission line analysis, Full-wave 3D analysis techniques such as FDTD
and Method of moments is beneficial. Experience correlating simulation
results with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum
analyzers is a plus.
Education: BSEE, BSCE and 5 years of experience.
Pedro Gonzalez, President
PMG Search
303.786.7100
pedro@xxxxxxxxxxxxx
303.499.4978 evening
303.443.0555 fax
web site: www.pmgsearch.com
"...Move up with us."
The information contained in this email is intended solely for the use of
the individual to whom it is addressed, and may contain confidential or
legally privileged information.
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
