[SI-LIST] Re: Interconnect Model for J971 (100MHz) Teradyne
- From: <Wolfgang.Maichen@xxxxxxxxxxxx>
- To: <jchurch@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 2 Dec 2011 07:38:59 +0000
Hello James,
I don't think there is an officially sanctioned, accurate model around (the
earliest Teradyne VLSI tester I know for sure a model exists for is the J973,
and even that one does not really model e.g. path losses). But for the
speed/bandwidth range the J971 works at it isn't too difficult to build your
own. It also depends what the goal of the model is - I assume to model the load
your DUT experiences? In this case, set the J971 channel to the desired state
(termination method etc.), then use a TDR-capable scope to obtain a TDR
profile. (be careful when terminating the channel with some non-zero voltage,
don't overload the TDR driver; thus you may want to use a DC block between TDR
instrument and tester input). From this profile you can then generate an
equivalent model using some software tool like Tektronix iConnect or similar. I
can help with that as well, I have some tool to half-manually create models
consisting of limited numbers of discrete components (Cs, Ls, Rs, transmission
lines etc.) that you can then easily use in PSpice, LTSpice or similar
simulators; again, the basis for model creation would be a TDR plot. Feel free
to contact me directly about that. Many more advanced simulation tools accept
S-parameter files, in this case a VNA is a good alternative to the TDR to
produce input data, although that gives only a "black box" model with little
insight into channel behavior, wheras a TDR lets you pinpoint the
characteristics, locations and sizes of any "troublemakers". (higher-end VNAs
often have a TDR option - basically real-time FFT - to produce TDR plots from
the S parameter sweeps).
That said, a first order model for most test applications would simply be a
50-Ohm transmission line with possibly some termination (resistive, diode
clamps, active load); the main parameter to determine here would be the line
length / prop delay (or not even that if the termination is matched 50 Ohms),
you may be able to get that from the tester's data sheet. For old, relatively
low-data-rate testers like the J971 that's probably sufficient for 99% of your
applications. Channel-to-channel differences are much more significant than the
relatively minor contributions of vias, relays etc. inside the tester.
Wolfgang
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Church, James
Sent: Thursday, December 01, 2011 5:59 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Interconnect Model for J971 (100MHz) Teradyne
Does anyone have an interconnect model lying about for a J971 Teradyne VLSI
Tester (circa 1995)?
Generating my own will take some time.
Regards,
James Church
Rockville Design Center
Rochester Electronics, Inc.
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