[SI-LIST] Re: Input spec difference between LVCMOS & SSTL
- From: steve weir <weirsi@xxxxxxxxxx>
- To: See Hour <yshour2001@xxxxxxxxx>
- Date: Wed, 21 Jul 2010 02:56:12 -0700
LVCMOS and LVTTL are legacy signaling standards that poorly controlled
both from impedance and timing standpoints. They are suitable only for
low signaling rates. If your timing is tight enough that you have to
worry about slew rates with LVCMOS / LVTTL you have likely overloaded
the bus. The remedies:
* If you can use a better controlled signaling technology.
* If you are stuck w/ LVCMOS / LVTTL often used with non-volatile
memories and other slow peripherals, then
* Divide the bus into more buffered segments OR
* Run at a lower signaling rate.
Steve
See Hour wrote:
> Thanks Hermann for the background.
>
> Because LVCMOS & LVTTL spec is DC, hence I never tested my CMOS/TTL buffer
> with AC waveform against spec.
> Another question comes into my mind. I believe VIH/VIL really dependant on
> input signal frequency (please correct me if I am wrong). So at frequency
> should we run at when testing for VIH/VIL AC? It is not stated in JEDEC AC
> test condition.
>
>
> --- On Wed, 21/7/10, Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
> wrote:
>
>
> From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
> Subject: Re: [SI-LIST] Input spec difference between LVCMOS & SSTL
> To: "See Hour" <yshour2001@xxxxxxxxx>
> Cc: si-list@xxxxxxxxxxxxx
> Date: Wednesday, 21 July, 2010, 2:48 PM
>
>
> Hello Gary,
>
> I can only give some background on SSTL:
>
> In memory development (where SSTL is used) Signal integrity is critical
> due to reflections and ringbacks. AC/DS spec was introduced to optimize
> Timing budget calculations for such "dirty" Waveforms.
> The basic thinking behind was to use the Energy tranmitted to the
> Receiver (but any area calculation was to complicated for a spec) and
> make sure the Receiver gets some kind of "overdrive" to allow fast
> switching.
> This is given by the AC level (+ derating) at the beginning of the eye.
> Once the Receiver is switched it will not switch back so easy. So the
> signal is allowed to come down to the DC level what again allows some
> reflections without violating the spec.
>
> Overall the target was to implement some physical Receiver behaviour
> into the SSTL spec that gives some more margin for timing budgets
> (especially on multidrop memory systems).
>
> Regards
>
> Hermann
>
>
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
> schrieb See Hour:
>
>> Hi Everyone
>>
>> Does anyone know why there is AC and DC VIH/VIL spec for SSTL & HSTL input
>> but there is only DC VIH/VIL spec for LVCMOS & LVTTL input?
>>
>> I couldn't find any related explanation from JEDEC documents. Appreciate if
>> you have any explanation or direct me to the right source. Thanks.
>>
>> Regards
>> Gary
>>
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>
>
>
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