[SI-LIST] Re: Impact of gap on stripline trace
- From: "Michael Khusid" <mkhusid@xxxxxxxxxx>
- To: <fdunlap@xxxxxxxxxxxxxxxxx>
- Date: Mon, 22 Sep 2003 09:41:45 -0400
Frank,
The basic physics of the problem: current always flows in loops. If a =
signal
current is flowing in the signal trace, it has to return somewhere in =
the
power/ground structure. In your example, the return current path has to =
jump
from I/O pwr to Ground plane somewhere. At DC, the path flows through =
the
I/O power supply. That works fine.=20
At high frequency, the return current either flows through a decoupling
capacitor between the power and ground, or "jumps" across the split =
through
radiating electromagnetic fields. In many cases, both effects take =
place.
The latter will be observed as EMI -- it is very common to have =
power/ground
splits as significant sources of EMI within the system. A good =
decoupling
capacitor strategy across the split provides an efficient path for =
return
currents.
So, there is no simple answer to your question - there is no X MHz below
which a split is OK and above which it is not OK. Ultimately, it comes =
down
to this: a plane split is a major discontinuity, and is as significant =
as a
discontinuity of the signal path impedance itself.
There are two ways to tackle this problem: either do simulations and
quantify how much discontinuity to the return current is added by the =
plane
split, or use trial and error to get the right values of decoupling
capacitors in the right places to smooth down the plane discontinuity. =
In
either case, the make it or break it "speed" will be determined by the
capacitor strategy that you employ.
Best regards,
----------------------------------------------------------------
Michael Khusid
Ansoft Corporation
SI/HF Application Engineer
=20
25 Burlington Mall Road, 6th floor
Burlington, MA 01803-4100
=20
Tel 781-229-8900 Ext. 134 =20
Fax 781-229-8624
---------------------http://www.ansoft.com ---------------------
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
Behalf Of Frank Dunlap
Sent: Friday, September 19, 2003 9:46 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Impact of gap on stripline trace
Consider a stripline signal trace that passes over a gap between a GND
plane and an I/O PWR plane. The stripline is covered above by a GND
plane.
=20
What is the impact of the gap? Is it totally unacceptable for the trace
to cross this gap (there is a continuous GND plane on the other side of
the signal trace), or are there "speeds (edge rates)" for which the gap
may be okay? If there are some "speeds" for which it is okay, how does
one determine those acceptable speeds?
=20
Does scale matter? In other words, if the gap is not acceptable for
feature sizes common in a PCB, might the gap be acceptable at the scale
of feature sizes common inside high-speed IC packages?
=20
Regards,
=20
Frank
=20
-----------| |-----------
| |
| |
| |
GND | | I/O PWR
| |
------------------------------
SIGNAL TRACE
------------------------------
| |
| |
| |
| |
| |
-----------| |-----------
=20
=20
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