[SI-LIST] Impact of gap on stripline trace
- From: "Frank Dunlap" <fdunlap@xxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 19 Sep 2003 18:46:10 -0700
Consider a stripline signal trace that passes over a gap between a GND
plane and an I/O PWR plane. The stripline is covered above by a GND
plane.
What is the impact of the gap? Is it totally unacceptable for the trace
to cross this gap (there is a continuous GND plane on the other side of
the signal trace), or are there "speeds (edge rates)" for which the gap
may be okay? If there are some "speeds" for which it is okay, how does
one determine those acceptable speeds?
Does scale matter? In other words, if the gap is not acceptable for
feature sizes common in a PCB, might the gap be acceptable at the scale
of feature sizes common inside high-speed IC packages?
Regards,
Frank
-----------| |-----------
| |
| |
| |
GND | | I/O PWR
| |
------------------------------
SIGNAL TRACE
------------------------------
| |
| |
| |
| |
| |
-----------| |-----------
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