[SI-LIST] IEEE CPMT Society Phoenix Chapter - 5/20 meeting announcement
- From: Sam Karikalan <sam_karikalan@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 15 May 2003 09:46:05 -0700 (PDT)
The May 2003 meeting of the IEEE - CPMT Society Phoenix chapter will be held on
Tuesday, May 20, 2003. Mr. Mark Sherwood, Principal Associate, CS&A, Santa
Clara, CA will be speaking on the topic of "Total Timing Budget - Packaging
Contribution".
Location: Motorola, 2100 E. Elliot Road, Tempe AZ (Group Conference Room)
Agenda: 5:30-6:00 p.m. - Social/Refreshments; 6:00-7:00 p.m. - Presentation;
7:00 p.m. - Dinner
IEEE Members & Non-members all are welcome to attend.
ABSTRACT
More than ever before, packaging designers and suppliers are now being
challenged to meet increasing performance and reliability expectations, at very
low cost. New device packaging options provide for a significant improvement in
electrical & thermal performance and accuracy. Manufacturing processes and
design tools are becoming more advanced to accommodate stringent physical
layout and routing requirements and to match simulations to the silicon.
As process capabilities reach 90nm and below, signal integrity and timing
demand greater attention. Jitter introduced by interconnects requires more
focus from a packaging engineer. This talk will be on signal integrity for
interconnects, with an emphasis on clock devices such as Oscillators/Timers and
Frequency Synthesizers. Discussions will focus on critical parameters such as
frequency, voltage swing, threshold voltage, impedance mismatch, waveform
inaccuracy and jitter. The presentation will address how standard JEDEC
packages, such as TSSOP, SOIC, QFP, PLCC, etc., have forced limitations in both
performance and accuracy in these types of devices. Advantages of low
inductance packages, such as BGA, MLF and E-Pad packages, will be presented.
Specific issues associated with higher I/O and pin count devices will also be
addressed.
BIOGRAPHY
Mr. Mark Sherwood is a Principal Associate at Consulting Services & Associates,
a Santa Clara, CA based company. His focus is test, measurement and accuracy
issues related to clock devices and his experience ranges from
military/aerospace to semiconductors and test & measurement. Mark was a
Business Development Director at Schlumberger ATE. He has also been with
Wavecrest and LeCroy Corporations. In semiconductors, Mark has held strategic
and technical positions at IDT, IMI and most recently Cypress Semiconductor.
Mark has worked extensively in multiple application segments such as Consumer,
PC/Data Processing, Datacom and Telecommunications.
For more information, please call any of the following officers:
Mali Mahalingam, Motorola (480) 413-5368; Sam Karikalan, Primarion (602)
659-4634
-------------------------------------------------------------------------------------------------------------------------------
Regards,
Sam Karikalan
Asst. Program Chair, IEEE CPMT Society - Phoenix Chapter
Primarion, Inc. 2507 W Geneva Dr, Tempe AZ 85282
Phone: (602)-659-4634 Fax: (602)-454-7220
E-mail: sam.kvk@xxxxxxxxxxxxx
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