[SI-LIST] Re: SDRAM data issues

  • From: "Nguyen, Mike" <Mike_Nguyen@xxxxxxxxxxxxxxxxx>
  • To: <jthomas@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 15 May 2003 10:00:06 -0700

Putting a probe adds capacitance to the data pin and increases Hold
time. You said the DRAM is very
Close to the ASIC, then make sure your clock is <=3D shortest data =
trace.
My guess is you have more margin on setup time.

Mike

-----Original Message-----
From: John Thomas [mailto:jthomas@xxxxxxxxxxx]=20
Sent: Thursday, May 15, 2003 8:41 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SDRAM data issues


Not a silly question at all.  Another one is the CAS latency being used.
A common mistake is to try to run in the CL2 mode but at the maximum CL3
frequency.

Best Regards,

John Thomas


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ken Cantrell
Sent: Thursday, May 15, 2003 9:28 AM
To: sankar.karuppannan@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SDRAM data issues



Sankar,
Silly first question - is the SDRAM rated for 115 MHz, or only 100 MHz?
Perhaps the probe capacitance is slowing the edge down enough for it to
work. Ken

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Sankar karuppannan
Sent: Thursday, May 15, 2003 6:34 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SDRAM data issues



Hi,
I am facing some problem in the SDRAM data lines. The problems are
whenever I am running more then 115MHz SDRAM read and write test is
failing. I connected logic analyzer to probe the signal then tests are
passing. In PCB SDRAM is placed very close to the ASIC. I do not know
the problem is due to the capacitance or ground. I gave sufficient
ground plane under the device. If any one knows the solution please help
me.

Thanks,

Sankar.K
Wipro Technologies,
72, Electronics City, Hosur Main Road,
Bangalore-561229.
Ph:+91-80-8520408 Extn: 4012/4031.


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