[SI-LIST] Re: IBIS simulation LVPECL
- From: Istvan Novak - Board Design Technology <Istvan.Novak@xxxxxxx>
- To: Bob Tarasewicz <Bob.Tarasewicz@xxxxxxxxxx>
- Date: Fri, 03 Oct 2008 12:24:05 -0400
Bob,
The one-lump R-L-C IBIS package model can capture the delay pretty
accurately but it
wont reproduce the step you see. The 100ps delay (200ps wide step)
corresponds to
about a centimeter interconnect in a board and organic package. If this
makes sense by
looking at your package, then you can trust your measurement. Whether
you need to
change the simulation environment depends on what kind of signaling you
simulate
and how critical this detail is for your overall simulation. Once the
phenomenon is
understood, you may just ignore it as long as you do not use the signal
anywhere
else other than at the far end, at the silicon receive input .
Regards,
Istvan
On 10/03/08 12:01, Bob Tarasewicz wrote:
> Istvan & Chris
> The step is about 200ps wide. I am measuring at vias right under
> the BGA pads. I don't know how accurate the package model is; the
> processor vendor provided it. Here is the package model info for the 2
> reciever pins AV21 and AU21
> AV21 Len=0 L=0.1n R=1.7m / Len=11391.99 L=0.4p C=0.11f R=0.06m /
> Len=0 R=3m / Len=0 L=0.4n R=2.54m /
> Len=0 R=3m / Len=0 L=0.08n R=0.04m C= 0.03p /
>
> AU21 Len=0 L=0.1n R=1.7m / Len=10354.47 L=0.4p C=0.11f R=0.06m /
> Len=0 R=3m / Len=0 L=0.4n R=2.54m /
> Len=0 R=3m / Len=0 L=0.08n R=0.04m C= 0.03p /
>
> I have to make some pretty significant changes in the receiver
> ibis model 'Define Package Model' in order for simulation to start showing
> a "step". If I change the 'Len' by a factor of 2x and the C by a factor
> of 5x (ie make Len=20000 and C=0.55f for both AV21 and AU21) , then
> simultion will show a "step". However, I'm not sure if making these
> kinds of changes to Len and C is still within a reasonable range or not.
>
> Thanks for your responses.
> Bob
>
>
>
>
>
> Istvan Novak - Board Design Technology <Istvan.Novak@xxxxxxx>
> Sent by: Istvan.Novak@xxxxxxx
> 10/03/2008 09:56 AM
>
> To
> Bob Tarasewicz <Bob.Tarasewicz@xxxxxxxxxx>
> cc
> si-list@xxxxxxxxxxxxx
> Subject
> Re: [SI-LIST] IBIS simulation LVPECL
>
>
>
>
>
>
> Bob,
>
> How wide is the step? Could it come from the round-trip delay from the
> pin connection where
> you measure, to the die, including possible via(s), package traces, bond
> wires -if any - ?
>
> Regards,
>
> Istvan
>
>
> On 10/03/08 10:42, Bob Tarasewicz wrote:
>
>> My simulations of an LVPECL net (apprx 3" long, 'Y' terminated just
>>
> beyond
>
>> receiver) do not seem to be correlating at all with in-lab measurements.
>>
>
>
>> In the past I've had very good luck with simulations agreeing pretty
>>
> well
>
>> with actual scope measurements; however, this is my first experience
>> simulating LVPECL. Is there a fundamental reason why perhaps IBIS
>>
> models
>
>> won't model the behavior of LVPECL accurately? Or is it that the faster
>>
>
>
>> edge rate of LVPECL is highlighting flaws/limitiations in my simulation
>> methodolgy and/or tool?
>> Simulations "at the pin" as well as "at the die" show nice
>>
> rising/falling
>
>> edges at the receiver. However, scope captures with a good diff probe
>> show a 'step' in the rising/falling edge at the receiver. The 'step'
>> looks like what one would expect halfway down a series-terminated net;
>>
> not
>
>> sure why I'm seeing a 'step' with an end-terminated net.
>>
>> Any guidance would be apprecitated.
>>
>> Bob Tarasewicz
>>
>>
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