Hi Sunil,
For IBIS model generation :
You can use Cadence Sigrity XtractIM tool.
For more information you can refer
http://www.cadence.com/products/sigrity/xtractim/pages/default.aspx
In case if you have transistor level netlist and would like to generate
behavioral model (IBIS), you can use Cadence Sigrity T2B tool. It outputs
models in IBIS 3.2, 4.2, and 5.0 formats. Power-aware behavioral driver
models generated by Sigrity T2B to maximize accuracy. You can use these
models for system level simulation as well. For more information you can
refer
http://www.cadence.com/products/sigrity/t2b/pages/default.aspx
For thermal parameter extraction, you can use Cadence Sigrity PowerDC
Package thermal characterization workflow which helps extracting
theta JA, theta Jb, theta-JC, @-resistor CTM models for single die and
multi-die packages as well as delphi model (JEDEC standard based).
Hope this helps.
Best Regards;
Jay shah
On Mon, May 30, 2016 at 11:37 PM, sunil bharadwaz <
dmarc-noreply-outsider@xxxxxxxxxxxxx> wrote:
Hello Friends ,
We are in the process of finalizing IC packages . I understand that the
lumped
R,L,C can be extracted by the IC package designer tools . We also
understandthat S-parameter files can be generated by tools like say , HFSS.
How do we generate IBIS models ? What tools are used here ?Similarly ,
which tools are helpful in giving Theta-JA (thermal resistance ) ,for these
IC packages .
Any suggestion regarding the material to be looked at or web links , would
be
very helpful .
Thanks in advance.
Best RegardsSunil.Bh
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