[SI-LIST] Re: IBIS Models for the Devices working at GHz speed
- From: "Kai Keskinen" <kalevi@xxxxxxxxxx>
- To: <darshanmehta2k@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 20 Dec 2005 17:29:02 -0500
There is no frequency limitation with IBIS models or spice based IBIS
simulators in principle. What does happen is that as the frequency and edge
rates increase, the package models must be distributed models, the simulator
has to have more accurate lossy line models, and your via models cannot be
simple lumped elements so that the stub effect is taken into account. I find
that with CML models in particular, it is difficult to generate the IBIS
model from the spice models and many chip vendors don't either know how or
don't want to make the investment. Good IBIS simulators can even use
pre-emphasis and IBIS allows you to set when the pre-emphasis kicks in with
driver schedule. I have received and used GHz speed CML IBIS models from
Intel, Freescale, and Mindspeed in Cadence Allegro PCB SI that agreed with
scope measurements reasonably well. You can also compare the performance of
the IBIS model and the Spice model in HSPICE and you will find they normally
agree if the IBIS model was correctly generated.
You just have to make sure that you have a good distributed line package
model (IBIS allows for that) and not lumped element and that your simulator
models lossy lines and vias properly.
My understanding is that Xilinx is going to be providing IBIS models for the
CML drivers in their Virtex devices soon but a Xilinx FAE should be able to
confirm that.
Chip vendors are in the business of making chips and it seems that the
intern or first person available gets to generate the IBIS model which is
why you see so many poor quality IBIS models that sometimes don't even pass
the parser. I have encountered I/O buffers where the Rx is supposed to have
on-die-termination and the Tx won't drive into the Rx. The Rx model is bad
because they don't understand the usage of the submodel statement in IBIS.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Darshan Mehta
Sent: Tuesday, December 20, 2005 1:59 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS Models for the Devices working at GHz speed
Hello SI Experts,
I have seen that for the devices working at GHz speed (for Example Vertex
FPGA) vendors generally prefer to provide encrypted Spice model and not IBIS
models. Are there any limitations of IBIS model at higher speed? Thanks!
Regards,
Darshan Mehta
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