[SI-LIST] Re: How to decide the sense point location of regulator for multi-load PCB design
- From: "Silvester" <silr@xxxxxxxxxxx>
- To: "'Ted H.Y. Chou'" <ted.hy.chou@xxxxxxxxxxx>
- Date: Tue, 30 Jun 2009 11:55:25 -0400
you can always try gooogling
http://www.google.com/search?q=optimizing+VRM+sense+lines&rls=com.microsoft:
en-us&ie=UTF-8&oe=UTF-8&startIndex=&startPage=1&rlz=
also, an article that touches on the subject
http://pcdandf.com/cms/content/view/5813/95/
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Ted H.Y. Chou
Sent: Monday, June 29, 2009 9:49 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] How to decide the sense point location of regulator for
multi-load PCB design
Dear SI/PI experts/gurus,
Does anyone have experiences of choosing the suitable sense point location
for regulator design of common motherboards? For achieving the least DC IR
drop for all loads, this (only one) sense point of regulator should be put
somewhere, (eg. in the center of these loads) not just around the source.
The difficult point is that these loadings are dynamic and the analysis
times of IR drop are also limited. Besides, due to high density layout
issue, the shorter feedback trace length is better. Could you tell me how
to do it?
Best Regards,
Ted Chou
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