[SI-LIST] Re: High Speed traces and connectors
- From: "Lakshmi N. Sundararajan - PTU" <lakshmi.s@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 11 Nov 2008 10:51:44 -0800
On further thoughts...
Connector is by itself creates a discontinuity. But
is the impedance presented by the connector to the driver
lower than the regular 50 ohms for each signal pins?
And so scrapping the GND/PWR plane under those signal, creates
an increased impedance much closer to 50 ohms?
Is that what this change achieves? This makes sense to me.
But is that the intention?
And as someone suggested are connector pads at these high frequencies
capactive or inductive? I though with those solder legs for pads,
each of the pads becomes inductive as frequency increases?
Am I not right? Any inputs on this?
Thanks,
-LN
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Lakshmi N.
> Sundararajan - PTU
> Sent: Tuesday, November 11, 2008 10:41 AM
> To: Suresh Subramaniam
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: High Speed traces and connectors
>
>
> I was thinking that at those speeds the solder pads make the
> connector/via
> connection inductive. Isnt that so?
>
> And these high speed traces are differential, so the return current is
> not through the GND plane.
>
> Anyways, scrapping the GND/PWR plane under those signal pads
> does alter
> impedance by changing capacitance as you all say.
>
> So, are we just targetting common mode signals with this change?
> So, common mode signals travelling through these diff traces will
> have a lower cap at the connector pad, which means increased
> impedance than would be? I still am not clear here how does this help.
>
> Any more insights.
>
> Thanks,
> -LN
>
>
>
>
> > -----Original Message-----
> > From: Suresh Subramaniam [mailto:ssubram@xxxxxxxxxx]
> > Sent: Tuesday, November 11, 2008 10:11 AM
> > To: Lakshmi N. Sundararajan - PTU
> > Subject: RE: [SI-LIST] High Speed traces and connectors
> >
> > Lakshmi,
> >
> > The reason for removing the PWR/GND or reference planes under
> > the connector pins is to reduce the capacitance. The
> > connector pin/via footprint is inherently capacitive.
> > Remember Z0 = Sqrt(L/C). It changes the impedance (creating a
> > discontinuity) especially at the data rates you mention. As a
> > matter of fact similar cutouts are recommended at the BGA to
> > board transition. You may want to refer to Appendix D of the
> > XFP specification to see the impact of various via footprints.
> >
> > Hope that helps.
> >
> > Best,
> >
> > Suresh Subramaniam PhD
> > Sr. Staff Engineer
> >
> > Tabula, Inc.
> > 3250 Olcott St.
> > Santa Clara, CA 95054
> > Ph: 408-986-9140 x:401
> > Fax: 408-986-9146
> > Email: sureshs@xxxxxxxxxx
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Lakshmi N. Sundararajan - PTU
> > Sent: Tuesday, November 11, 2008 9:58 AM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] High Speed traces and connectors
> >
> > Hi Team,
> > I had a curious review mentioned on my board for high speed
> > traces for which I could not get a satisfactory explanation.
> >
> > For all high speed traces from a connector, the review
> > mentioned to remove GND/PWR plane from under the *signal
> > pads* under connector.
> > Even for the PCIE connector, for all the signal pads, the
> > GND/ PWR plane was requested to be removed.
> > Now, these are 6Gig and 5Gig high speed signals. If there
> > isnt GND/PWR plane then definetely I would assume there isnt
> > any reference plane for return current.
> >
> > So, can you experts suggest, whether this is a right thing to
> > do and if so why?
> >
> > Thanks
> > -LN
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