[SI-LIST] Re: High Speed traces and connectors
- From: "Lakshmi N. Sundararajan - PTU" <lakshmi.s@xxxxxxxxxxx>
- To: "Suresh Subramaniam" <ssubram@xxxxxxxxxx>
- Date: Tue, 11 Nov 2008 10:40:38 -0800
I was thinking that at those speeds the solder pads make the
connector/via
connection inductive. Isnt that so?
And these high speed traces are differential, so the return current is
not through the GND plane.
Anyways, scrapping the GND/PWR plane under those signal pads does alter
impedance by changing capacitance as you all say.
So, are we just targetting common mode signals with this change?
So, common mode signals travelling through these diff traces will
have a lower cap at the connector pad, which means increased
impedance than would be? I still am not clear here how does this help.
Any more insights.
Thanks,
-LN
> -----Original Message-----
> From: Suresh Subramaniam [mailto:ssubram@xxxxxxxxxx]
> Sent: Tuesday, November 11, 2008 10:11 AM
> To: Lakshmi N. Sundararajan - PTU
> Subject: RE: [SI-LIST] High Speed traces and connectors
>
> Lakshmi,
>
> The reason for removing the PWR/GND or reference planes under
> the connector pins is to reduce the capacitance. The
> connector pin/via footprint is inherently capacitive.
> Remember Z0 = Sqrt(L/C). It changes the impedance (creating a
> discontinuity) especially at the data rates you mention. As a
> matter of fact similar cutouts are recommended at the BGA to
> board transition. You may want to refer to Appendix D of the
> XFP specification to see the impact of various via footprints.
>
> Hope that helps.
>
> Best,
>
> Suresh Subramaniam PhD
> Sr. Staff Engineer
>
> Tabula, Inc.
> 3250 Olcott St.
> Santa Clara, CA 95054
> Ph: 408-986-9140 x:401
> Fax: 408-986-9146
> Email: sureshs@xxxxxxxxxx
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lakshmi N. Sundararajan - PTU
> Sent: Tuesday, November 11, 2008 9:58 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] High Speed traces and connectors
>
> Hi Team,
> I had a curious review mentioned on my board for high speed
> traces for which I could not get a satisfactory explanation.
>
> For all high speed traces from a connector, the review
> mentioned to remove GND/PWR plane from under the *signal
> pads* under connector.
> Even for the PCIE connector, for all the signal pads, the
> GND/ PWR plane was requested to be removed.
> Now, these are 6Gig and 5Gig high speed signals. If there
> isnt GND/PWR plane then definetely I would assume there isnt
> any reference plane for return current.
>
> So, can you experts suggest, whether this is a right thing to
> do and if so why?
>
> Thanks
> -LN
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> //www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> //www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
