[SI-LIST] Re: HCSL
- From: Ray Anderson <ray.anderson@xxxxxxxxxx>
- To: "Thomas Biggs" <tnbiggs@xxxxxxxxx>
- Date: Thu, 9 Sep 2010 16:14:03 -0700
Tom-
As far as I was able to determine, the only place that the HCSL spec is
documented is/was in the FB-DIMM spec.
Seems strange, but I guess the JEDEC guys didn't think it warranted a
standalone document.
A number of various manufacturer's data sheets have info on HCSL voltage
swing etc., but they all seem to lead back to the FB-DIMM document.
If anyone knows of a more definitive spec I'd like to hear about it.
-Ray
Raymond Anderson
Senior Signal Integrity Staff Engineer
Programmable Platforms Development
Silicon Technology Group
Signal Integrity and Package Development Department
Xilinx Inc.
2100 Logic Drive
San Jose, California 95124
(408) 626-6277
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Thomas Biggs
Sent: Thursday, September 09, 2010 3:53 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HCSL
Ray Anderson had asked this question back in 2005, though I saw no
reply.
Is there some kind of official HCSL (high-speed current steering logic)
specification? If so, where can I find it?
I see references to it in the JEDEC JESD8-18A FB-DIMM spec and in some
PCIe
specs, but have found no spec for HCSL by itself.
-tom
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