[SI-LIST] Re: Fw: PCIe 3.0 Clock Jitter Tool
- From: Joseph.Schachner@xxxxxxxxxxxxxxxxxx
- To: Hermann.Ruckerbauer@xxxxxxxxxxxxx
- Date: Wed, 11 Feb 2015 12:14:59 -0500
Hi, Herman. I think the issue is that you are referring to "the Spec" but
actually there are at least THREE specs we need to consider. (There are
many more specs related to PCIe, but these are the ones that relate to
this question):
1) Base spec: Definitely has specs on the clock. This spec is all about
chips. It does not comprehend "system board" and "add in card", those are
form factors defined in CEM.
2) Card Electro-Mechanical (CEM): Defines "add in card" and "system board"
form factors, and defines requirements at the PCIe connector that is the
interface between them. Derived from Base.
3) Test spec (made by PCIE Serial Enabling Group, SEG): Derived from CEM,
this test spells out test procedures to ensure CEM requirements. The
documents written by companies about how to use their equipment to do
"compliance tests" are implementing the procedures defined in the Test
spec.
So, you are correct! The Base spec does have requirements on the clock,
and any clock chip used should be tested to them, and must meet those
requirements. That's why I wrote "If you are building a system board (or
root complex on something) sure, you want to test the clock."
But then I went on to talk specifically about CEM requirements and Test
spec procedures. I believe the thinking is that once you have a board,
you have gotten beyond where that Base spec clock requirements should have
been checked. The intent is to test for interoperability of Add In Cards
and System Boards. Part of the workshop actually is "interop" testing -
where every Card present for testing is tried in every system present for
testing.
There are many other tests at a workshop; they test protocol, receiver
sensitivity, ability to do the equalization negotiation at speed and end
up in a state that works to 1e-12 BER, TX signal quality and presets...
and probably one or two more that I'm not thinking of right now. All of
the electrical tests are defined at the PCIE connector and therefore the
requirements cannot be the same as base spec requirements. Instead, the
CEM requirement are derived from Base spec requirements. I think we should
all be OK with the idea that the CEM is not repeating all the Base spec
requirements.
By the way, in addition to automating compliance tests I think every scope
company does have some kind of automation of at least a subset of Base
spec tests (those that are appropriate to measure on a scope, that is).
Base spec electrical testing generally requires a break out board, and s
parameter files that are use do de-embed the response of that board so
that measurements are referred back to the package pins. Or, I think for
some measurements, you also want to de-embed the package model to
extrapolate back to the die. That board is likely to be unique to the
manufacturer, for their chip. So Base spec testing requires more setup
and requires that you obtain s parameter files for your breakout channel
before you can get to testing.
--- Joe S.
From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx,
Date: 02/11/2015 10:02 AM
Subject: [SI-LIST] Re: Fw: PCIe 3.0 Clock Jitter Tool
Sent by: si-list-bounce@xxxxxxxxxxxxx
Hello Joe and others,
yes, your answer is very interesting especially as I had tested in the
past several boards with PCIe Gen1/2 devices (from 2 major device
vendors) that failed the clock jitter spec significantly.
Several of them passed the Signal quality tests (dual port measured),
but one could clearly see the degradation of the Signal quality based on
clock jitter.
At least in one case the signal compliance test was failing too (and I
think the device vendor has in the meantime removed Gen2 support from
the feature list)
I had loooong discussions with the device vendors on this one.
My point of view:
There is a separate clock spec, and somebody thought about this when
writing the Spec. So if I violate the spec this is a compliance fail.
The vendors point of view was similar to your comment: the signal
quality tests are relevant and will take care of the clock jitter as well.
But in this case: why is the spec not adjusted to this thinking ?
I don't want the clock tests to be removed from the spec, as it is very
important to execute them for analysis. Otherwise it is very difficult
to distinguish between an issue on the signals and an issue on the clock
(this is the drawback of the dual port testmethodology .. it delivers a
Pass/FAil, but it is difficult to analyze the source of the issue).
So currently we have a spec that could have a fail in the clock jitter
test, but passing the signal quality test.
For me, this situation is classified as "compliance Fail" as long the
clock tests are not downgraded to "informative" status ...
Any feedback on this is welcome!
Hermann
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Am 11.02.2015 um 15:45 schrieb Joseph.Schachner@xxxxxxxxxxxxxxxxxx:
> Hi, Nagar.
> The previous answer (that you need to be a member of PCI SIG to get the
> Clock tool) is correct.
> By the way, it is not the "PCIE 3.0 Clock Jitter Compliance Measurement
> Tool". What the web site page about testing tools says about it is:
> (FYI Only) PCI Express Clock Phase Jitter Test Software: ClockTool
version
> 1.3:
> Software package that analyzes captured reference clock data to PCI
> Express 1.1 CEM specification or the PCI Express Base 2.0 specification.
> Software runs on Windows XP*
>
> The text above is from the PCIe 1.1 section. Below is text from the
PCIe
> 2.0 section:
> PCI Express Clock Phase Jitter Test Software: ClockTool version 1.3.
> Same as for PCI Express 1.1a
>
> This tool is not referred to in the PCIe Gen3 section of that web page.
>
> Since you thought this was a "PCIE 3.0 ... Compliance Measurement Tool",
I
> just want to add a few words about what PCIe TX compliance testing
really
> is. If you are building a system board (or root complex on something)
> sure, you want to test the clock. However, at PCI compliance workshops
we
> stopped running the clock signal through the intel Clock Jitter tool I
> think back at Gen 2, and we certainly don't do it for Gen 3. For Gen2
and
> Gen3 the Test spec mandates that we acquire the clock and the data
signal
> simultaneously, and SigTest measures jitter on the data signal relative
to
> the simultaneously acquired clock signal. See any company's MOI or the
> test spec itself, you'll see that.
>
> The reason for this change from PCIe 1.1 should be obvious. Jitter on
the
> data and jitter on the clock could both be "in spec" magnitudes, but if
> the phase of the jitter was not tightly correlated the data relative to
> clock jitter could be higher than either, instead of less (as you would
> expect if they moved together). It is from experience gained during
PCIe
> 1.1 testing that the CEM group realized they needed to change the
> methodology to measure data to clock jitter, because that is what
matters
> - that is what the receiver may need to deal with.
>
> I hope this is interesting. If you are working with PCIe I encourage
you
> to join the PCI SIG. You would get access to all the specs, all the
> approved MOIs, all the test tools, and you would be able to listen in
to
> work group meetings, if you want to.
>
> -- Joseph Schachner
> Senior Software Engineer
> Teledyne LeCroy
>
>
> From: "nagar ashish" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted
sender
> "ashish_nagar1@xxxxxxxxx" for DMARC)
> To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>,
> Date: 02/10/2015 11:24 PM
> Subject: [SI-LIST] PCIe 3.0 Clock Jitter Tool
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
>
>
> I am looking for PCIe 3.0 Clock Jitter Compliance measurement  tool.
Read
> about many are using Intel Clock Jitter Tool for the same purpose. Need
> help to find how to procure the tool, tried PCI-SIG, intel, doing google
> also.....but no luck so far.
> Anyone used the tool ? How to procure the tool ? and is that the
standared
> compliance tool for PCIe 3 Clock Jitter ??
> Ashish
>
>
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