[SI-LIST] Re: Fw: Decoupling capacitor,
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Bill Owsley <wdowsley@xxxxxxxxx>
- Date: Sun, 08 Jul 2007 21:21:50 -0700
Bill only if we assume that the interconnect cavity is substantively
thick and that the load die has negligible capacitance. This becomes a
very interesting problem when trying to design stuff that has a lot of
fast switching that also wants to live on a cheap four layer PCB. The
processor manufacturers found out a long time ago that a combination of
a lot of die capacitance and in package capacitors is the only way to
keep those loads fed at frequencies above where arbitrary caps placed
right up against and/or under the chip package attached through a thick
cavity can be sufficient.
Regards,
Steve.
Bill Owsley wrote:
> "Eddy how far away a capacitor can be depends on the interconnect between
> the capacitor and the load."
>
> Well distance does seem like a factor. The cap is meant to be close
> enough to maintain the voltage at an acceptable level and to do this
> it has to be within a distance determined by the speed of propagation
> in the substate of interest in order to supply charge an enough to
> maintain the voltage within the defined levels/limits, say for example
> 1/20 of the supply.
> So how far away is 1/20, or some fraction of the voltage, given a
> speed of propagation, then the caps should not be any further away
> than that distance, and large enough to supply the charege needed.
>
>
>
> */steve weir <weirsi@xxxxxxxxxx>/* wrote:
>
> Eddy how far away a capacitor can be depends on the interconnect
> between
> the capacitor and the load.
>
> Ideally this is something that we engineer
> by design. Unfortunately it is often something that is handled by
> rote
> practice. In the past rote practice often overengineered the power
> system. These days more often than not it underengineers it. I
> suspect
> that failure analysis will find power and thermal issues at the
> heart of
> Microsoft's current $1.15 billion recall.
>
> Steve.
> Eddy wrote:
> > "a temporary power feeder in case of power shortage"
> > I think that is nice job description for a decoupling
> > capacitor. :-)
> > The problem is impedance of power lines. Distance
> > means inductance and inductors resist fast changes of
> > current. When a CMOS buffer changes state, it goes
> > together with a current spike in the power supply.
> > Depending upon the impedance of the power supply,
> > there will be a "negative spike" (dip) in the power
> > supply voltage. This dip not only slows down the
> > transition of the CMOS buffer itself but also affects
> > other circuits tied to the same power supply nearby. A
> > current spike is not just "a frequency" but rather a
> > wide spectrum of frequencies. Most chips have lots of
> > different circuits all creating total chaos ("noise")
> > on the power supply. For most chips it is vital to
> > have a decoupling capacitor as close as possible
> > between the power supply pins of your circuit.
> > Sometimes 10mm distance is already too far. The most
> > used decoupling capacitor value has to be 0.01uF or
> > 10nF.
> >
> > Eddy
> > Fremont CA
> >
> > --- M Sridhar wrote:
> >
> >> I have a doubt about Decoupling capacitor, I
> >> understand that decoupling capacitor is used to
> >> decouple power supply to the device, so it acts as a
> >> temperery power feeder in case of power shortage.
> >> My doubt is how to know at what frequency the power
> >> fluctuation would happen?
> >> From were we may get this information.
> >>
> >> Thanks,
> >> Sridhar.
> >>
> >>
> >
> >
> >
> >
>
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