I'm excited to share my experience overcoming PCIe4 test challenges with
Rohde & Schwarz at their Milpitas office.
Details and register at:
https://www.rohde-schwarz-usa.com/12122017_Registration.html
*** December 12 (Tuesday) 2017 ***
Session 1: Methodologies for Evaluating PCIe4 Reference Clocks
Review of the clock jitter requirements for 16 Gb/s PCIe Gen 4 links.
The higher speeds of these links require substantially lower jitter
margins such that the RMS jitter requirement is near the limits of
traditional oscilloscope based measurements. This session will cover
timing measurement techniques, the limits of different measurement
methods and specific measurement requirements per the latest draft of
the standard. The relationship between phase noise and jitter will be
explained and techniques for determining RMS timing jitter will be
compared.
Session 2: Jitter Measurement Example using Phase Noise Techniques
Phase noise measurements have long been the preferred method of
evaluating oscillators for RF applications. These instruments are very
sensitive to even small timing variations and the frequency domain side
bands allow one to directly determine the signal to noise ratio. The
high sensitivity of this method is also a benefit for clocks for many of
the same reasons.
Session 3: Power Integrity and Its Impact on Clock Jitter
A primary contributor to timing jitter on clock signals is noise on the
power plane. The primary sources of this noise are switching transients
on the power supply and PDN impedance flatness. Oscilloscope methods for
evaluating noise on power rails will be presented and the relationship
between this noise and jitter will be explained.
Session 4: Evaluating the Timing Jitter of High Speed Serial Data
Signals Using S-Parameters
The high signaling rates employed in PCIe Gen 4 are pushing the
frequency carrying capability of traditional FR4 pc board materials. The
standard employs both channel equalization and error correction to
compensate for signal distortion caused by the channel. The application
of s-parameter measurement of the channel using a network analyzer will
be discussed along with techniques for estimating the eye diagram using
the measured channel response will be presented.
Hope to see you there,
Gary Giust
JitterLabs
1551 McCarthy Blvd, Milpitas, CA 95035
(408)627-6454
www.jitterlabs.com
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