I'd like to add my 2ct.
The major reason for auto negotiation is that neither loss, dispersion nor
distortion is known by the chips. There has been silicon that needs the
de-embedding and equalization settings fixed in hardware, and that required to
put in the link settings to every single connection and leaves you totally
inflexible. In systems with mixed manufacturers hardware, there is just no way
to tell the chips up front what link performance it will be dealing with.
Especially for FR4, the dispersion is what ruins most of the signal, and what
is very easily fixed with de-embedding and equalization. Multiple reflections
from impedance discontinuities can't really be fixed by software. Only the
signal runtime differences caused by discontinuities can be fixed.
Regarding moisture I'm opposed to Joseph. I only know a handful of materials
that are affected by moisture (all non-FR4 type of plastics like LCP or PI),
but almost all materials are affected by temperature.
Regarding impedance of traces I can say that the target impedance doesn't
necessarily have to be the chip impedance or recommended technology impedance
to work best. There have been many papers about this topic by Intel and others.
I Personally use lower impedance than specified by the link technology because
it reduces reflections and doesn't add much losses. But for really high speeds
(>25Gbps), impedance becomes more critical and should be watched case by case.
At those speeds, even more critical is the copper roughness because it adds
much more losses than impedance mismatch.
BR
Gert
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Schachner, Joseph
Sent: Tuesday, January 29, 2019 3:43 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] FW: PCIe Gen3/Gen4 Presets optimization
I think you should ask this on the PCI SIG's web site, there is a forum for
members to ask questions.
But anyway, when the link is first established the equalization negotiation
happens. It does not happen again unless there is an error. A typical error
is sync loss, where the receiver does not see a legal two-bit header for a 128
bit packet. Legal is either 01 or 10. This makes the link go through
Recovery state again, where it redoes negotiation. It may end up at a
different preset on each end. Or it may not end up at any preset: the taps can
be adjusted. And, if it can't find any suitable equalization, it may end up
at a lower speed.
Yes, it is required to do this when the link comes up. Let me tell you some
reasons why that is a good thing.
1) If your board is some version of FR4, with bundles of glass fibers embedded
in resin layers, then the impedance and distortion of signals will vary
depending on whether it has a significant run over a glass bundle, or not. Or
whether it slowly crosses glass bundles at a slight angle - essentially passing
impedance changes. These effects will vary from board to board, so best eq
will be different.
2) Some PC board materials are sensitive to humidity; they absorb water
molecules and that changes the board's characteristics. Best eq may be
different in dry and moist environments. If a board is saturated, and the PC
(or whatever) gets warm as it runs, the board may dry out over a day of use.
If the change is significant and causes one of a class of errors, then it's
good that best EQ will be re-found.
3) You probably know that the width you specify for a trace is not guaranteed
to be perfect. It may vary within tolerance. The thickness of the layers may
vary. If you test for trace impedance I'm sure there is an acceptable
tolerance, perhaps +/- 15% of nominal. So, that pretty much is a guarantee
that trace impedance will vary from board to board, at least across
manufacturing batches. That could cause best eq to be different.
I hope these are not news to you. You can check each one of these, you will
find they are true. So I really do think that having to negotiate best
equalization on every boot, and on certain types of communication error, is
actually very good thing.
--- Joe S.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Praveen Kumar
Sent: Monday, January 28, 2019 7:10 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCIe Gen3/Gen4 Presets optimization
Hi All,
Since PCIe Gen3/Gen4 does dynamic equalization what is the point of figuring
out optimum preset values ? (some For plug and play (involving System
Board/Addin_Card types of PCIe Devices) definitely it doesn't make sense
because users might introduce additional cables between RC & EP so different
scenarios need different presets but if the Root Complex and End points are on
same PCB is it required to figure out optimum preset values and override (using
SW) the preset values determined during dynamic equalization?
Note: I'm not saying Transmitter/Receiver Equalization Validation is not needed.
Praveen
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