[SI-LIST] Re: EMC Issue at 266 MHz
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: <a.ingraham@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 2 Mar 2004 08:46:00 -0700
Jean-Pierre,
I think Brent DeWitt's approach is the first step, try and find out where
it's coming from. If this proves unproductive, don't forget about enclosure
and/or cable length resonances.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ingraham, Andrew
Sent: Monday, March 01, 2004 10:53 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EMC Issue at 266 MHz
Even if the clock waveforms were perfectly symmetrical ...
If on-chip circuits are clocked by both rising and falling edges of the
input clock, then you've got a strong even harmonic. There could be
radiation from the on-chip circuits, or from the supply lines to/from the
chip.
Also, keep in mind that there could be small amounts of intermodulation
between the various frequencies present, which include not only 50 and 66.7
MHz, but also 16.7 MHz or something lower at the PLL's phase detector. This
lower frequency may not appear on any of the PLL's pins, but it could be
causing a weak modulation of the VCO output.
Regards,
Andy
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