[SI-LIST] Re: Does the signal reference to the vddq will increase the power plane noise?

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: Ravinder.Ajmani@xxxxxxxx
  • Date: Tue, 25 Sep 2012 11:22:06 -0700

In differential signaling, the effects are identical with one 
exception:  The receiving amplifier sees the net disturbances introduced 
as common mode noise.  The CMR, and CMRR of the receiving amplifier then 
determine the impact.
Steve.
On 9/25/2012 11:15 AM, Ravinder.Ajmani@xxxxxxxx wrote:
>
> Hi Steve,
>
> How does this affect differential signalling.  In one of our designs, 
> DQS and Clock are referenced to 1.8 V plane on the substrate, whereas 
> on the PCB they are referencing Ground plane.
>
> Thanks.
>
>       
> Regards
> Ravinder Ajmani
> HGST, a Western Digital company
> ravinder.ajmani@xxxxxxxx
>
> HGST, a Western Digital company       5601 Great Oaks Pkwy.
> San Jose, CA 95119-1003_
> __www.hgst.com_ <http://www.hgst.com/>
>
>
>
>
>
> *steve weir <weirsi@xxxxxxxxxx>*
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
> 09/25/2012 03:40 AM
> Please respond to
> weirsi@xxxxxxxxxx
>
>
>       
> To
>       si-list@xxxxxxxxxxxxx
> cc
>       
> Subject
>       [SI-LIST] Re: Does the signal reference to the vddq will increase the 
> power plane noise?
>
>
>
>       
>
>
>
>
>
> To answer your question, you have to know what the signal reference is
> where it is launched, and what the receiver references where the signal
> is sensed.  If a signal is launched referenced to Vss, then
> rereferencing it to something else like Vddq does three things:
>
> 1) Injects signal current into the Vddq / Vss network.
> 2) Inserts the local impedance of the Vddq / Vss network at the
> transition between references into the channel impedance.
> 3) Couples the difference voltage that is between Vddq and Vss at the
> receiver to the signal potential that the receiver sees.
>
>
> Steve.
> On 9/25/2012 1:07 AM, liewluping@xxxxxxxxxxxx wrote:
> > Hi all:            this question maybe too simple but confuse me 
> many weeks: if the signal reference to the io power plane,for example 
> ,ddr3@1866mbps,do the power noise will increase compare to the gnd 
> refernce only design which only contains ssn noise? Or what will 
> happened if we measured at the boards,or the die? Does the transition 
> energy couple to the vddq plane will change the result or not?  thanks 
> a lot.                 liu luping
> >
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>
> -- 
> Steve Weir
> IPBLOX, LLC
> 150 N. Center St. #211
> Reno, NV  89501
> www.ipblox.com
>
> (775) 299-4236 Business
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-- 
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV  89501
www.ipblox.com

(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax

All contents Copyright (c)2012 IPBLOX, LLC.  All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records
and notify the sender.



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