[SI-LIST] Re: Does the signal reference to the vddq will increase the power plane noise?
- From: Ravinder.Ajmani@xxxxxxxx
- To: weirsi@xxxxxxxxxx
- Date: Tue, 25 Sep 2012 11:15:00 -0700
Content-Type: text/plain; charset="US-ASCII"
Hi Steve,
How does this affect differential signalling. In one of our designs, DQS
and Clock are referenced to 1.8 V plane on the substrate, whereas on the
PCB they are referencing Ground plane.
Thanks.
Regards
Ravinder Ajmani
HGST, a Western Digital company
ravinder.ajmani@xxxxxxxx
5601 Great Oaks Pkwy.
San Jose, CA 95119-1003
www.hgst.com
steve weir <weirsi@xxxxxxxxxx>
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09/25/2012 03:40 AM
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[SI-LIST] Re: Does the signal reference to the vddq will increase the
power plane noise?
To answer your question, you have to know what the signal reference is
where it is launched, and what the receiver references where the signal
is sensed. If a signal is launched referenced to Vss, then
rereferencing it to something else like Vddq does three things:
1) Injects signal current into the Vddq / Vss network.
2) Inserts the local impedance of the Vddq / Vss network at the
transition between references into the channel impedance.
3) Couples the difference voltage that is between Vddq and Vss at the
receiver to the signal potential that the receiver sees.
Steve.
On 9/25/2012 1:07 AM, liewluping@xxxxxxxxxxxx wrote:
> Hi all: this question maybe too simple but confuse me many
weeks: if the signal reference to the io power plane,for example
,ddr3@1866mbps,do the power noise will increase compare to the gnd
refernce only design which only contains ssn noise? Or what will happened
if we measured at the boards,or the die? Does the transition energy couple
to the vddq plane will change the result or not? thanks a lot. liu
luping
>
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