[SI-LIST] Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance

From: Peter Sørensen <pso@xxxxxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: Sun, 19 Aug 2007 23:46:58 +0200

At present I am trying to analyse and fix the impedance of my digital =
power
supplies in our new PCB construction.
This turns out to be more complex than most digital designers think.
I have read a number articles and a book so far, but I have not found =
the
solution. It just made me able to do simulation in a spreadsheet and
visualize the problem.

Modern SMD capacitors have low ESR =3D high Q. They also have some =
inductance,
but do not forget the VIA inductance which often is bigger than the
component itself. Traces are totally forbidden in my world due to
inductance. Large caps like 1210 get one via on each side of the pad.
These stray inductors combined with the capacity generates zeros and =
poles.
The zero's are great they reduce the impedance to the ESR value plus
resistance in VIA's, equal to a very low impedance at some frequencies.
Using many capacitors increases the frequency area with a low impedance.
Power Planes places close to GND planes are great, they makes capacity =
with
zero inductance for any frequency that matters, but they only works at =
high
frequencies especially if you have small planes.

I have made some simulations showing that with a small power plane of 2
square inch (a core voltage use by one BGA) I get a huge pole at
900MHz. The impedance is above 0.05 ohms from 100MHz and up 3 GHz. The
question is how far down do IC's need a low impedance.
At 3 GHz is does not matter, at this frequency only decoupling in =
silicium
will work due to inductance in package etc.
But what about the 100MHz, I believe a low impedance must be provided =
for
many IC's up to about 300MHz or even more.
Eg. This core is running at 400MHz and I would like a low impedance in =
that
range.
The IC's supplier do not specify supply impedance, many have PCB layout
guidelines but often they can not be copied.
For this one I used one 1210 100uF and an array of twenty 0402 220nF. =
Adding
more caps would help but there is not room.
The simulation result also depends on what you estimate your via's
inductance and resistante to be.

What really would help would be capacitors with higher ESR =3D low Q. =
They
would lower the poles impedance and raise the zero impedance.
Do they exist?
Properly not, I have not beeen able to find them.

Using leaded components is not an option, they may have lower Q but they
will also have more inductance and use more space etc.

Combining two or more values of array caps in 0402 house like 220nF+ =
10nF
does not help much and generate a new pole between the two zero's, this =
poel
is lower but also at a lower and more critical frequency.

To me it looks impossible to garantee a low impedance of below 0.05 ohms =
or
better at the intire frequency range of interest.

I belive the reason that most digital designs still works is that the =
poles
do not match the load frequencies in most applications.
I believe most designers still do as usual and then cross their fingers =
and
hope they do not have any poles at critical frequencies.
How many of you do power impedance analyses during design?

It looks like I am back in the old days where we build a prototype and =
then
started to find the correct components values?

Best regards
Peter S=F8rensen


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7:27 AM
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Follow-Ups:
- [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance
  - From: istvan novak

[SI-LIST] Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance

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