[SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance

  • From: "Lars Juul" <write2larsj@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 23 Aug 2007 15:28:57 +0200

I guess the next question on everybody's mind (on mine, anyway) becomes:
What's the lead time and cost of a new interposer design for your specific
pinout plus added board analysis services grasciously provided by various
high speed consulting companies who built your interposer?

As you need to make a call between that and doing a couple of your own
prototypes, with cleverly placed probe points and decoupling options,
building your own knowledge base and design rules for the PCB process you
use.

Lars

2007/8/21, Julian Ferry <julian.ferry@xxxxxxxxxx>:
>
> Scott McMorrow is presenting a webinar this Thursday on the interposer
> approach that Steve mentioned.
>
> For anyone interested, there is still time to sign up.
>
> Samtec's PowerPoser(tm) Interposers Webinar is scheduled for Thursday,
> August 23, 2007 at 11:00 AM EST.
>
> Register at:
>
> http://www.connectorwizard.com/Webinars.aspx
>
>
> Julian Ferry
> High Speed Engineering Manager
> Samtec, Inc.
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of steve weir
> Sent: Monday, August 20, 2007 4:31 PM
> To: write2larsj@xxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Decoupling of digital power i PCB's, how do we
> avoid pole peaks in the impedance, how far up in frequency do we need low
> impedance
>
> Lars, Peter, today you need to collect papers. In a few months Istvan
> will have a couple of books out on power delivery that will hopefully
> reduce the need to hunt for tidbits here and there. Istvan also has many
> excellent papers on his web site. He's got a lot of the papers by people
> once of SUN as well as himself, like Larry Smith and Ray Anderson. The
> X2Y web site www.x2y.com has a number of decoupling / bypass papers, as
> does the Teraspeed site, www.teraspeed.com from yours truly. There is
> also useful information in Lee's first book, "Right the First Time". Lee
> self publishes so you have to go to his web site for that
> www.speedingedge.com.
>
> Simulators generate hallucinations that are sometimes useful and
> sometimes useless. It mostly goes back to garbage in / garbage out. But
> with good source data, and an understanding of what a given simulator
> assumes and how it goes about its evaluation you can get useful results
> from those packages. To do so, the most important information you need
> to engineer a reliable power system by design is often the most
> difficult to obtain: detailed information about the: package parasitics,
> internal storage, real current profile, and actual voltage requirements
> of the IC's that you intend to use. We can build a power system that
> looks like a dead AC short on the PCB and actually end up worse off at
> the die than with a higher impedance power system. I cannot emphasize
> enough the importance of either obtaining the IC information from your
> vendor, or deriving it through measurements. [SHAMELESS PLUG ALERT!]
> This is something that we do in Teraspeed's Portland labs. For FPGA's
> Samtec and Teraspeed have developed an interposer product that
> essentially shrink wraps the power system for those IC's, so you don't
> have to chase that rabbit down the hole.
>
> When it comes to implementing the power system resonances between
> different MLCC capacitors is usually a low priority issue. Below about
> 20MHz you can analyze it with good accuracy using any of many 1D
> parallel admittance spreadsheet tools out there, including: one Istvan
> offers for free on his web site, a freebie from Altera, and one you can
> buy from UltraCad. Above about 20MHz the spatial effects of the
> interconnect changes what your IC die sees compared to the PCB planes.
> Here any number of tools are useful, including commercial products, or
> free software like Fast Henry. If you have a decent model for each of
> your significant ICs, and software that is at least 2D aware, then you
> can reliably predict the plane and IC power delivery. But if you don't
> have decent models of your IC's, your models are going to become
> fantasies where it counts: resonances created by interaction of the IC
> die with the PDN. This tends to happen at frequencies well below bypass
> cap network to plane cavity resonance, or the loaded PCB modal
> resonances. A $100,000 software tool cannot fix faulty assumptions.
>
> For anything that you are going to do with capacitors, mounted
> inductance is the enemy from DC to daylight. More mounted inductance
> translates to more parts, and higher Q in each resonance, be it between
> the VRM and bulk caps, bulk caps and MLCCs, MLCCs of different values,
> or MLCCs and IC die, or MLCCs and the plane cavities. If you are going
> to become religious about anything to do with PDN design, battling
> inductance is a worthy crusade. Multiterminal caps like X2Y(tm)'s ( I
> consult to X2Y(tm) ) offer a lot of help in the battle against
> inductance. An exciting recent development is that Samsung is now making
> X2Y(tm) caps up to 2uF total in an 0603 package.
>
> So my bottom line is: Get IC data. Understand and limit resonances.
> Terminate inductance with extreme prejudice.
>
> Good luck.
>
>
> Steve
>
> Lars Juul wrote:
> > Hej Peter,
> > A brief comment on your last statement:
> >
> >> It looks like I am back in the old days where we build a prototype and
> then
> >>
> > started to find the correct components values?
> >
> > Even though you can literally spend 100K's of $$$ on simulation tools
> that
> > can extract your board layout and simulate your decoupling network, you
> > always have to make the call whether it's
> >
> > a) cheaper and faster to build a few prototypes, building your own set
> of
> > decoupling design rules based on your already good understanding of
> linear
> > systems.
> >
> > or
> >
> > b) preferable to come up with a simulation flow where the results are
> > correllated to the boards you produce, enabling you to quickly verify
> your
> > layout.
> >
> > Either way, you need to build a knowledge base of do's and don'ts and
> that
> > experience doesn't come for free.
> >
> > a) is the choice if you're focusing mostly at perfecting one product at
> a
> > time, and if you or your test and measurement folks are experienced,
> able to
> > effectively pinpoint the defects of a design.
> >
> > b) is the choice if you have a steady flow of new designs coming
> enabling
> > you to constantly correllate your results and have fewer redesigns. The
> > initial matching of simulation and measurements can be a painful,
> lengthy
> > affair, though.
> >
> > My point is, the EDA folks will always try to convince you that using
> their
> > tools you'll always have hole-in-one designs, but for me prototyping
> remains
> > as the most secure way of ensuring your board works.
> >
> > And I'd rather put my money on something that works in the lab rather
> than
> > in a simulator.
> > But again, that's just my ?0.02.
> >
> > Best regards,
> > Lars
> >
> > 2007/8/20, istvan novak <Istvan.Novak@xxxxxxx>:
> >
> >> Peter,
> >>
> >> A few quick answers/observations:
> >>
> >> 1) How far down the IC needs low impedance?
> >> The core power distribution circuit from the chip's perspective is
> >> probably OK with a high
> >> impedance at 900MHz; the package and/or silicon has to take care of
> that
> >> frequency range.
> >> SI and EMI may suffer though; if you happen to route signal traces
> >> referencing this core
> >> plane, the signal may suffer too much.  Similarly, dependent on the PCB
> >> and system
> >> constructions, the resonance may create EMI problem.
> >>
> >> 2) Higher ESR capacitors; do they exist?
> >> In ceramic MLCCs, they start to appear on the market.  You can look at
> >> the DesignCon
> >> 2007 presentations at http://home.att.net/~istvan.novak/papers.html
> >>
> >> 3) How many of you do power impedance analyses during design?
> >> Well, at large OEMs we have to do at least some sort of analysis,
> >> sometimes very detailed
> >> designs and validations.
> >>
> >> In general, the problem you notice is the resonance between the
> >> inductances of the bypass
> >> capacitors resonating with the static capacitance of the planes.  There
> >> are a few ways of
> >> helping it:
> >> - you can make the static capacitance lower (this pushes out the
> >> resonance frequency).
> >> You can lower the capacitance by placing the power/ground planes
> further
> >> away, but
> >> this also increases the plane inductance; this is not your first
> >> choice.  You can. however,
> >> make the plane shape as small as possible (with some boundary area
> >> left), this will
> >> minimise capacitance.
> >> - as you pointed out, you can increase the ESR of parts.  This does not
> >> change the
> >> resonance frequency, but reduces the peak.  Dependent on what
> >> mid-frequency
> >> impedance you need, you can simply use R-C components with
> low-inductance
> >> layout, or you can consider the high-ESR MLCCs.
> >> - finally, a brute force solution, not requiring special part is to
> >> overwhelm the inductance
> >> of the plane.  If cumulatively your capacitors present an inductance,
> >> which is about 1%
> >> of the plane inductance, the resonance peak is mostly gone.  To achieve
> >> this, you can
> >> place the power/ground planes close to the surface, so that via
> >> inductance is less, or
> >> can use multiple vias for each capacitor, use low-inductance
> capacitors,
> >> like reverse
> >> geometry, X2Y or multi-terminal capacitors.
> >>
> >> Regards,
> >>
> >> Istvan Novak
> >> SUN Microsystems
> >>
> >>
> >> Peter Sørensen wrote:
> >>
> >>
> >>> At present I am trying to analyse and fix the impedance of my digital
> =
> >>> power
> >>> supplies in our new PCB construction.
> >>> This turns out to be more complex than most digital designers think.
> >>> I have read a number articles and a book so far, but I have not found
> =
> >>> the
> >>> solution. It just made me able to do simulation in a spreadsheet and
> >>> visualize the problem.
> >>>
> >>> Modern SMD capacitors have low ESR =3D high Q. They also have some =
> >>> inductance,
> >>> but do not forget the VIA inductance which often is bigger than the
> >>> component itself. Traces are totally forbidden in my world due to
> >>> inductance. Large caps like 1210 get one via on each side of the pad.
> >>> These stray inductors combined with the capacity generates zeros and =
> >>> poles.
> >>> The zero's are great they reduce the impedance to the ESR value plus
> >>> resistance in VIA's, equal to a very low impedance at some
> frequencies.
> >>> Using many capacitors increases the frequency area with a low
> impedance.
> >>> Power Planes places close to GND planes are great, they makes capacity
> =
> >>> with
> >>> zero inductance for any frequency that matters, but they only works at
> =
> >>> high
> >>> frequencies especially if you have small planes.
> >>>
> >>> I have made some simulations showing that with a small power plane of
> 2
> >>> square inch (a core voltage use by one BGA) I get a huge pole at
> >>> 900MHz. The impedance is above 0.05 ohms from 100MHz and up 3 GHz. The
> >>> question is how far down do IC's need a low impedance.
> >>> At 3 GHz is does not matter, at this frequency only decoupling in =
> >>> silicium
> >>> will work due to inductance in package etc.
> >>> But what about the 100MHz, I believe a low impedance must be provided
> =
> >>> for
> >>> many IC's up to about 300MHz or even more.
> >>> Eg. This core is running at 400MHz and I would like a low impedance in
> =
> >>> that
> >>> range.
> >>> The IC's supplier do not specify supply impedance, many have PCB
> layout
> >>> guidelines but often they can not be copied.
> >>> For this one I used one 1210 100uF and an array of twenty 0402 220nF.
> =
> >>> Adding
> >>> more caps would help but there is not room.
> >>> The simulation result also depends on what you estimate your via's
> >>> inductance and resistante to be.
> >>>
> >>> What really would help would be capacitors with higher ESR =3D low Q.
> =
> >>> They
> >>> would lower the poles impedance and raise the zero impedance.
> >>> Do they exist?
> >>> Properly not, I have not beeen able to find them.
> >>>
> >>> Using leaded components is not an option, they may have lower Q but
> they
> >>> will also have more inductance and use more space etc.
> >>>
> >>> Combining two or more values of array caps in 0402 house like 220nF+ =
> >>> 10nF
> >>> does not help much and generate a new pole between the two zero's,
> this =
> >>> poel
> >>> is lower but also at a lower and more critical frequency.
> >>>
> >>> To me it looks impossible to garantee a low impedance of below 0.05ohms
> >>>
> >> =
> >>
> >>> or
> >>> better at the intire frequency range of interest.
> >>>
> >>> I belive the reason that most digital designs still works is that the
> =
> >>> poles
> >>> do not match the load frequencies in most applications.
> >>> I believe most designers still do as usual and then cross their
> fingers =
> >>> and
> >>> hope they do not have any poles at critical frequencies.
> >>> How many of you do power impedance analyses during design?
> >>>
> >>> It looks like I am back in the old days where we build a prototype and
> =
> >>> then
> >>> started to find the correct components values?
> >>>
> >>> Best regards
> >>> Peter S=F8rensen
> >>>
> >>>
> >>>
> >>>
> >>>
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