[SI-LIST] Re: Daisy chain topology for DDR2 addressing signals?
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: emcesd@xxxxxxx
- Date: Mon, 24 Sep 2012 13:19:13 +0200
Hello *,
in this case it might be not just SI but also some Controller internal
timings.
it might be require to match CLK and DQS in order to fulfill tDQSCK (so
make delay CLK - DQS very small). But for the read the delay CLK + DQS
defines when the Controller can switch on it's receivers. this timing is
often part of the training sequences. It might be difficult to find a
valid length window that fulfills the Requirements for CLK - DQS and the
reqiurements for CLK + DQS at the same time.
I have seen issues in training sequences for DDR3 and can imagine that
fo rDDR2 controllers this is much more critical ..
Hermann
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Am 24.09.2012 12:30, schrieb Tesla:
> The ADS also has a DDRx Design kit,
> Wish you lucky.
>
> Thanks.
>
>
>
>
>
>
> At 2012-09-24 17:43:47,"Shao, Peng" <Peng_Shao@xxxxxxxxxx> wrote:
>> If you can fully handle all the DDRx bus timing and SI quality, then need
>> not care about what kind of topology it is.
>> For DDRx timing verification and SI quality checking, the best tools is DDRx
>> Wizard from HyperLynx. You may ask for a demonstration from your local AE.
>> Very easy and efficient!
>>
>> Shaopeng
>> PCB and SI Consultant
>>
>>
>> Hi Venkat
>> You would be better off using a T-topology for address/control with
>> termination at each brach end It would be easier to length match the whole
>> interface
>>
>> Regards
>> Farooq Bhatti
>>
>> Sent from my iPhone
>>
>> On Sep 17, 2012, at 10:19 PM, "Venkatarao.s" <venkatarao.S@xxxxxxxxxx> wrote:
>>
>>> Hi all,
>>>
>>>
>>> For 72 -bit DDR2 interface, we are using 5 DDR2 devices each having
>>> 16-bit data width .All five DDR2 address signals are shared, So can I
>>> use Daisy chain topology for DDR2 addressing signals?
>>>
>>>
>>>
>>> Please suggest topology.
>>>
>>>
>>>
>>> Regards,
>>>
>>> Venkat
>>>
>>>
>>>
>>>
>>>
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