[SI-LIST] Re: Daisy chain topology for DDR2 addressing signals?
- From: Tesla <emcesd@xxxxxxx>
- To: Peng_Shao@xxxxxxxxxx
- Date: Mon, 24 Sep 2012 18:30:49 +0800 (CST)
The ADS also has a DDRx Design kit,
Wish you lucky.
Thanks.
At 2012-09-24 17:43:47,"Shao, Peng" <Peng_Shao@xxxxxxxxxx> wrote:
>If you can fully handle all the DDRx bus timing and SI quality, then need not
>care about what kind of topology it is.
>For DDRx timing verification and SI quality checking, the best tools is DDRx
>Wizard from HyperLynx. You may ask for a demonstration from your local AE.
>Very easy and efficient!
>
>Shaopeng
>PCB and SI Consultant
>
>
>Hi Venkat
>You would be better off using a T-topology for address/control with
>termination at each brach end It would be easier to length match the whole
>interface
>
>Regards
>Farooq Bhatti
>
>Sent from my iPhone
>
>On Sep 17, 2012, at 10:19 PM, "Venkatarao.s" <venkatarao.S@xxxxxxxxxx> wrote:
>
>> Hi all,
>>
>>
>> For 72 -bit DDR2 interface, we are using 5 DDR2 devices each having
>> 16-bit data width .All five DDR2 address signals are shared, So can I
>> use Daisy chain topology for DDR2 addressing signals?
>>
>>
>>
>> Please suggest topology.
>>
>>
>>
>> Regards,
>>
>> Venkat
>>
>>
>>
>>
>>
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