[SI-LIST] Re: 回复: DDR-simulation

  • From: "Vani Kaushik" <vanisekharan@xxxxxxxxx>
  • To: kranthi.paturi@xxxxxxxxxxxxxxxxxx
  • Date: Thu, 31 Aug 2006 11:07:10 -0700

Hi Kranthi,
If your problem is just about simulating a multi board topology, then all it
comes to is modelling the connector which forms the interface between the
sodimm and the main board. Of course the degree of accuracy is much higher
when one is able to extract the topology right off the board files for the
main design and the sodimm when performing simulation using specctraquest.
But if these are not available an understanding of elements relevant SI in
the topology under sonsideration could help molde the topology at a decent
level of accuracy.

Stackup play a role in multi board for defining the trace characteristics on
individual boards, and vias on the same.
It will mostly be a case of simulating boards with different stackup in
multi board scenario.
the components in topology to be considered for modeling are:
1. Transmission line characteristics of traces
2. connectors
3. Vias
4. the end buffer models
5. Any termination required for the toplogy, this will be determined by the
kind of topology you use, like if it is daisy chaining or not.
I hope my mail will be of help in understanding the problem better.

Thanks and warm regards
Vani


On 8/23/06, ±ò Áú <alonger2002@xxxxxxxxxxxx> wrote:
>
> I once did such a simulation with cadence SQ tools, first the simulation
> is for multi-board.you need to creat a design link to make connection
> between the Main board and the DIMM board. with cadence tool,for the EBD
> module you just need to translate to .DML and used the DML file to make
> connection when creat the design link.you need not to read the EBD
> file(there will be several files) if you just want to the simulation with no
> intention to know more about the EBD module,I think you need to find a spec
> of how to do such a simulation with mentor tool.it will be easy..
>
> But for my simulation,I do it according to the process defined in cadence
> SI tool Spec,As cadence tool does not support the EBD module well,i can not
> got the signal top correctly in cadence SigXplorer. the siganl trace module
> is wrong and the receiver module is just a buffer module with no package and
> so on.I contact cadence FAE but can not resolve this problem. Finally I
> read the EBD module. base on my understand with the help from SumSung and
> Cadence, I creat the top manual.....
>
> So wish you good luck and the mentor tool will be no issue for such a
> simulation.
> kranthi <kranthi.paturi@xxxxxxxxxxxxxxxxxx> дµÀ£º
> Hi,
>
> I have an "MT9VDDT12872HG" DDR sodimm module interface on my board for
> which I have to check the signal integrity.I downloaded the following
> Zip file "mt9vddt6472hg-40bd2_ebd" for the IBIS format.this contained
> the following files in it
>
> 1) mt9vddt6472hg-40bd2 ---->EBD source document
> 2) eeprom_nc ---->VeriBest IBIS Librarian
> 3) t27b_ddr400 ---->VeriBest IBIS Librarian
>
> I have mentor graphics - signal vision/signal analyzer tool for
> simulation.
>
> The EBD document contained the SODIMM details while "t27b_ddr400.ibs"
> file contained the IBIS files of different components.
>
> In the "mt9vddt6472hg-40bd2 ---->EBD source document" there are [Path
> Description]s given.In this, What are the units considered for values
> given in "Len" section.Please explain what parametres to be considered
> and how to start with doing the simulation of SODIMM interface with the
> IBIS files provided because the SODIMM module is with a different
> stackup and my design is with a different stackup.
>
> In case any one worked on this, Please reply ASAP!
>
> Thanks & Regards,
> Kranthi Kumar Paturi,
> Design Engineer,
> Indus Teqsite (Pvt) Ltd,
> Chennai, INDIA-600033,
> Ph: 91-44-24848702(Extn:221)
>
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