[SI-LIST] Re: Setup-Hold Equations for Source Synchronous Design

  • From: "Hill, John" <John.Hill@xxxxxxxxxx>
  • To: <Cclewell@xxxxxxxxxxxxx>, <nrpatel@xxxxxxxxxxx>
  • Date: Thu, 31 Aug 2006 16:08:00 -0400

Hello all,

I am reading page 149 of this book right now and am a bit confused. It
is describing SSTL_2 and declares that Vin must reach 405 mV above Vref.
Can someone tell me how you get the number 405?

BTW, the book identifies Vih(ac) and Vil(ac) at 0.31, but the
specification has 0.35. Is this an old specification?

http://download.micron.com/pdf/misc/sstl_2spec.pdf#search=3D%22sstl_2%22

Best regards,

John



=20

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-----Original Message-----

From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Clewell, Craig
Sent: Monday, August 14, 2006 3:31 PM
To: 'nrpatel@xxxxxxxxxxx'
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Setup-Hold Equations for Source Synchronous
Design

Try Digital Techniques for High-Speed Design ~ Tom Granberg
ISBN#0-13-142291-X

-----Original Message-----
From: nrpatel@xxxxxxxxxxx [mailto:nrpatel@xxxxxxxxxxx]
Sent: Monday, August 14, 2006 3:14 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Setup-Hold Equations for Source Synchronous Design


Hello all,
Can someone point me out to a good reference that explains the setup and

hold margin calculations for a source synchronous design like DDR?
Did not have much luck googling.

Thanks,
Nikhil=20



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