[SI-LIST] Re: DDRII write problem!!
- From: Chandrashekhar Kalyanaraman <ckalyan@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 18 Aug 2009 20:17:34 -0700
Hi Tina,
Is this 1.8V DDR-II? Do you have a VTT (termination voltage)?
If there is a VTT, the DQ line will sit at the VTT voltage whenever it is idle.
My guess is that is what you are seeing, but 0.5V doesn't make sense for
DDR-II.
Regards
KC
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of TinaWu
Sent: Tuesday, August 18, 2009 7:38 PM
To: si-list@xxxxxxxxxxxxx
Cc: 吳亭瑩
Subject: [SI-LIST] DDRII write problem!!
Dear Sir,
I simulated the DDR write and the waveform is bad.
Here, I found the input(DQ) of DDR chip.
There are 3 states - logic 0 (0V)¡Blogic 1 (1V) and
the other state 0.5V. Is the phenomena right??
Thanks in advance!!
BRs,
Tina
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